Saturday, November 24, 2012

Starting the Instruction Decode board

If I'm going to have boards to work on by Christmas I need to get them submitted in the next week or so. It's not the highest thing on my priority list, but I did make a start this week.

I started by beginning the layout of the Instruction Decode board. Here's a snapshot of its current state, with about 80 components yet to be placed and essentially no routing done:

The schematic shows the OPR decoder above the OPA decoder, with the final combinational logic below that. This makes sense if the ALU is the next thing down, but in my implementation the ALU is on another board reached through the smaller connector. This led me to rearrange the groups a bit so the final combinational logic is between the OPR and OPA decoders. The groups of components nearest the larger connector form the OPR and OPA "registers"; since these registers are updated for each instruction cycle, transmission gates capture the state of the data bus on MOSFET gate capacitances rather than using flip-flops.

The structure of the combinational logic doesn't lend itself to tight packing, so I went ahead and repartitioned the design as described in the post A little re-partitioning. This moved the 61 components of the ALU timing circuits off the Instruction Decode board and onto the ALU board where they belong. To avoid making the ALU board more dense, I moved the 60 components of the external chip select logic off the ALU board and onto the Timing and I/O board.

Not bad for a day's work.

Tuesday, November 13, 2012

It leads to the Source...

I've finally had time to post the Verilog source for the 4004 CPU to my OpenCores project.

The sources posted synthesize for the Xilinx Spartan-3e using the WebPack edition of ISE 12.4 XST, and simulate using ISim. They also synthesize using the Lattice iCEcube2™ tool chain for the HX40 series, though I haven't tried loading that yet.

I haven't yet posted the test bench code, nor have I posted the code implementing the 4001 ROM chip. I'll get around to this sooner or later, I promise.

I have this fantasy of finishing the layout of the remaining boards in time to populate them over the christmas holidays, but realistically that's unlikely to happen. It's somewhat more likely that I'll do some layout during the holidays, get them fabricated in January, and work on them over the following months.