- CLK1 == 1'b1
- D[0:3] == 4'b1111
- M12+M22+CLK1~(M11+M12) == 1'b1
Experiments with the world's first microprocessor
and other electronic explorations
Wednesday, December 30, 2015
Incrementer shoot-through analysis
The problem I'm investigating occurs when the incrementer circuit attempts to pull a signal high and low at the same time. This happens whenever these conditions are all true:
Tuesday, December 29, 2015
Shooting the Incrementer
The next oddity I though I'd investigate is the always-on pass transistor in the CLK1 signal in the IP incrementer. You can spot it on the far right edge and near the bottom of the picture below; look for the FET with its gate hard-wired to Vdd.
When I built my IP board I blindly followed the i4004 design, and the incrementer seemed to work during my testing described in my post Like a Phoenix back in September 2012. But this FET has always been a source of confusion. Why would the chip designers do this?
I dreamed up various theories. The one that seemed most likely was a critical timing condition, as a signal passing through such a FET would incur some small delay. Another thought was some sort of ringing in the chip, with this FET acting as a snubber. I thought about putting my IP board on the bench and see what effect this FET might have, but I'd be probing blindly.
So what function does this signal (N0325 in the simulator) perform? It seems to cause some signals to be driven high that may or may not be pulled to ground later, a common dynamic logic technique used in the DRAM array and elsewhere. But while stepping the simulator through the first carry operation (00F to 010) I noticed something strange: some of the signals go into "undefined" states (circuits colored gray in the picture). This means that they're being driven both high and low at the same time. This can result in "shoot-through", where Vdd is connected to Vss through a low-resistance path. Ouch!
This seems to be the case in the screen capture I posted above. This particular capture occurred at cycle 1586 but it's not a unique situation. Yet I can't imagine Intel could meet power dissipation targets with large shoot-through currents. So what's going on?
Maybe there isn't a low-resistance path. That might happen if the FET driving the signal high isn't turned on fully. How would you keep this FET from turning on fully? You'd lower the gate voltage. That pass transistor might have that effect; the output voltage would be limited to a maximum of Vdd - Vgs. Remember that CLK1 (and CLK2) are driven externally much closer to Vdd than other inputs. Unfortunately I really don't know the gate threshold voltage of the P-channel MOSFETs used in the real i4004.
Wouldn't I have seen signals going into undefined states in my testing? The Verilog version of the incrementer is behavioral, not gate-level, so it wouldn't have shown up there. It's not a situation I considered when testing the actual IP board, and my logic analyzer's buffer limitations prevented me from seeing the carry out of the first nibble to the second. I can't even say for sure that the nibble-carry works.
Once again, I seem to have a mystery on my hands. I'll have to put my IP board on the bench and see whether the incrementer handles carries from one nibble to the next properly. I'd like to probe the circuits that go to "undefined" states with my oscilloscope, but I'll have to give some thought to how to trigger on it.
I dreamed up various theories. The one that seemed most likely was a critical timing condition, as a signal passing through such a FET would incur some small delay. Another thought was some sort of ringing in the chip, with this FET acting as a snubber. I thought about putting my IP board on the bench and see what effect this FET might have, but I'd be probing blindly.
So what function does this signal (N0325 in the simulator) perform? It seems to cause some signals to be driven high that may or may not be pulled to ground later, a common dynamic logic technique used in the DRAM array and elsewhere. But while stepping the simulator through the first carry operation (00F to 010) I noticed something strange: some of the signals go into "undefined" states (circuits colored gray in the picture). This means that they're being driven both high and low at the same time. This can result in "shoot-through", where Vdd is connected to Vss through a low-resistance path. Ouch!
This seems to be the case in the screen capture I posted above. This particular capture occurred at cycle 1586 but it's not a unique situation. Yet I can't imagine Intel could meet power dissipation targets with large shoot-through currents. So what's going on?
Maybe there isn't a low-resistance path. That might happen if the FET driving the signal high isn't turned on fully. How would you keep this FET from turning on fully? You'd lower the gate voltage. That pass transistor might have that effect; the output voltage would be limited to a maximum of Vdd - Vgs. Remember that CLK1 (and CLK2) are driven externally much closer to Vdd than other inputs. Unfortunately I really don't know the gate threshold voltage of the P-channel MOSFETs used in the real i4004.
Wouldn't I have seen signals going into undefined states in my testing? The Verilog version of the incrementer is behavioral, not gate-level, so it wouldn't have shown up there. It's not a situation I considered when testing the actual IP board, and my logic analyzer's buffer limitations prevented me from seeing the carry out of the first nibble to the second. I can't even say for sure that the nibble-carry works.
Once again, I seem to have a mystery on my hands. I'll have to put my IP board on the bench and see whether the incrementer handles carries from one nibble to the next properly. I'd like to probe the circuits that go to "undefined" states with my oscilloscope, but I'll have to give some thought to how to trigger on it.
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