What's a couple layers among friends?

Ever notice that some projects seem most interesting when there's something else you're avoiding doing? Yeah, me too.

November 2016 will mark the 45th anniversary of the release of the Intel 4004. This is enough of a significant anniversary to make me feel a bit of a kick in the ass to complete the remaining four boards of the CPU this year.

FDV301 turn-off characteristics

At first I thought it might be illuminating to add a resistor between the source of Q5 and Vss so I could see how much current was making it from Vdd though both Q4 and Q5 to Vss. I've been playing with the results for over a week now and just couldn't come up with a consistent explanation for my results.

I take that back. I've determined that there's so much noise between Vdd and Vss alone on the solderless breadboard that attempts to measure small signals accurately is extremely difficult. This despite a generous helping of bypass capacitors ranging from 0.1uF ceramics and 10uF tantalums to 200uF electrolytics. What seems to work best is using the oscilloscope in difference mode to measure the voltage across a single resistor. This seems to null out most of the Vdd fluctuations.

Eventually I moved R4 so it sat between Q4 and Q5 and measured the voltage across it. What I see is less than 2mA (200mV across 100 ohms) through that resistor during the low-to-high output transitions, and essentially nothing during the high-to-low transitions, regardless of which FET I use for Q4. That kinda kills shoot-through current a culprit.

To try to figure out where the current is going I modified the test circuit to put R4 in series with the gate of Q4. To minimize differences between my test circuit and the actual push-pull driver I reconnected the drain of Q4 to Vdd, and the source of Q5 to Vss.

Non-inverting Push-Pull driver characteristics

Now let's take a look at the non-inverting push-pull driver circuit. There are two significant differences. First, the inverter formed by Q3/R3 is now in the path of the low-side driver rather than the high-side driver. Second, since it's the high-side driver that needs the higher voltage provided by the bootstrap load, R2 is now 2.2K and R3 is 4.7K.

Inverting Push-Pull driver characteristics

I haven't had time or motivation to dig into the shoot-through analysis described in the previous few posts, but I thought I'd look into another aspect of the same problem: the push-pull drivers.

These come in two basic categories: inverting and non-inverting. I then have two implementations of each, depending on whether the high-side driver is an FDV301 or a BSS83 FET. Each of these requires separate evaluation. In this post we'll look at only the inverting flavors, leaving the non-inverting flavors for the next post.

Whittling down the suspect count

All I wanted to do as a first pass was to identify those that need a closer look and which don't. But since I don't have an index of which FETs are used for what purpose I had to take a look at all 105 FETs connected to Vdd to identify them. Searching for a FET by part identifier and recognizing one of the common configurations I listed in the previous post only took a few seconds per part.

It turns out there are eight tri-state drivers, reducing the number of suspect circuits from 20 to 12. Here's the list:

• T0667 -- ACC D0 input latch precharge
• T0668 -- ACC D1 input latch precharge
• T0669 -- ACC D2 input latch precharge
• T0670 -- ACC D3 input latch precharge
• T0857 -- I/O D3 output(?) precharge
• T0858 -- I/O D2 output(?) precharge
• T0859 -- I/O D1 output(?) precharge
• T0860 -- I/O D0 output(?) precharge
• T1333 -- unknown
• T1477 -- unknown
• T1510 -- ALU D1 precharge
• T1512 -- ALU D3 precharge

I recognized what some of these do from developing the Verilog implementation and I've noted as appropriate. Of course I'll still check the timing of these. I may even double-check the timing of the IP and SP column sense precharge FETs while I'm at it.

Looking for more potential short-circuits

Although the shoot-through problem in the incrementer will be fairly easy to address, I'm concerned that similar situations could exist elsewhere. I consulted with Lagos Kintli, the author of the awesome 4004 simulator, about modifying it to automatically detect these situations. We've concluded that it's not technically feasible, but I might be able to analyze the internal state log the simulator already provides.

This got me thinking about the scope of the problem. For this problem to occur, there must be an active pull-up transistor with the drain connected to Vdd. This can be determined by searching the simulator's netlist; there are 104 of them. Of these:

• 58 are used in push-pull drivers (see below).
• 12 are used in Read Precharge circuits in the Instruction Pointer array.
• 8 are used in Read Precharge circuits in the Scratch Pad array.
• 6 are used in the IP Incrementer; one of these is a problem.
• An undetermined number 8 are used in Tri-state push-pull drivers.

All of the above have been analyzed. Although it's possible, perhaps even likely, that there may be brief transients as the push-pull drivers switch state, these will be extremely brief; unlike the problem in the incrementer which persists for as long as CLK1 is high.

That leaves 20 12 potential problems to be reviewed. That's a manageable number for a manual search.

A second i4004 design flaw?

The designers of the Intel 4004 CPU were innovative and talented, but like all humans they make mistakes. One, affecting the Instruction Pointer counter, I described in a previous post. The more I look at this, the more I think this is a second mistake.