Power planes revisited

This posting has been rewritten for clarity.

This evening, while sitting at a stoplight, I was mentally reviewing the various techniques for routing power and ground addressed in High-Speed Digital Design, A Handbook of Black Magic. One of the techniques mentioned was the "power and ground grid" (pg. 197), where ground traces run horizontally between ground busses along the vertical edges, and the power traces run vertically between power busses along the horizontal edges. The authors of the book do not favor this technique for a variety of reasons they explain in detail. But then they're writing about systems with rise times of 1ns or less, and that's an entirely different world.

In my case, the fall times of my signals are short, measuring just a few nanoseconds on my breadboard. On the breadboard I've seen situations where signals fall well below ground level, rebound to almost +1V (uncomfortably close to Vgs[th] for the the FDV301N), then fall back to ground. Probing the Instruction Pointer board, with its unbroken ground plane, has shown none of that nonsense. This argues strongly for an unbroken ground plane for the other boards.

In contrast, the rise times of my signals are quite long. The fastest of the rise times seem to occur in circuits like that to the right, where a B-type pull-up resistor (2.2K in my implementation) drives the high-side of a push-pull driver. Even in this circuit, though, the rise time is about 25ns from ground to +1V and follows an RC curve above that. This suggests that routing power as in the "power and ground grid" technique wouldn't cause a problem.

While contemplating the best way to achieve this, the most obvious solution in the world came to mind. Deciding that I don't need a power plane is different than having to route power traces individually. All I have to do is be careful when routing signals on this layer to avoid creating any islands or placing VDD vias in narrow areas.