More thoughts on i4004 clocking

Much of my concern, as expressed in previous posts like A clocking nightmare, have been based on the assumption that reflections on one of the two clock lines could cause multiple edges and thus multiple clocking of edge-sensitive circuits. While this would be correct with modern edge-clocked flip-flops, I don't think it applies to the original 4004 circuitry.

Let's start by reviewing the execution cycle of the 4004 CPU. Bear in mind that since the original 4004 was implemented using PMOS technology, the signals in this diagram are asserted when they are "low".

MCS-4 Basic Instruction Cycle

This shows the two clock phases, Φ1 and Φ2, that alternate without overlapping. It also shows there are eight phases in the execution of a 4004 instruction: A1, A2, A3, M1, M2, X1, X2, and X3.

Internally, these phases are identified by eight signals, only one of which will be asserted at any one time. This is the classic "one hot" scheme, and is implemented using a shift register through which a single "hot" bit propagates through the down the register.

Since I used NMOS FETs in my implementation, for the remainder of this narrative I'm going to refer to the asserted state as "high".

Here's a screen shot of the schematic showing the circuitry that implements the first four bits of this shift register:

The top two horizontal signals are CLK1 (topmost) and CLK2. The upper row of components forms the shift register, while the lower row are inverting drivers. T1016, T1015, and T1014 form three bits of a 7-bit NOR gate that controls the input to the first stage of the shift register and causes it to self-initialize.

To understand the operation, let's assume we're in the middle of execution phase A1, after CLK1 has been deasserted but before CLK2 is asserted. The signal A12 is asserted, turning on T1016 and pulling the bottom of R1750 to ground.

When CLK2 is asserted in phase A1, T0011 turns on, allowing T1016 to pull the gate of T0994 to ground turning it off. At the same time T0010 also turns on, allowing the A12 driver pull the gate of T0992 high turning it on. When CLK2 is deasserted both T0011 and T0010 turn off, capturing the charges on the gates of T0994 and T0992. However, neither A12 nor A22 will change state.

When CLK1 is asserted in phase A2, T0993 turns on, allowing R1961 to pull the input to the A12 inverting driver high, and thus A12 goes low. At the same time T0991 turns on, allowing T0992 to pull the input to the A22 inverting driver low, causing A22 to be asserted.

This same circuitry is repeated for the rest of the 8-bit shift register.

This is also typical of other circuitry in the 4004 CPU: the two clocks force the CPU to step forward in an orderly fashion. It doesn't matter how many edges are seen on either CLK1 or CLK2 as long as they don't overlap, and as long as each is asserted for long enough to allow the charge on the "upstream" side of the pass gates to propagate through to the "downstream" side.

This really reduces my worries about the clock signals. For maximum flexibility I may use a different pair of pins on my main connector for each of the planned boards. This will allow the maximum flexibility when it comes to the clock driver configuration.