i4002 DRAM array operation

To match the operation of the i4002 RAM chip in my Verilog emulation, I needed to understand exactly how the RAM array is accessed.

The i4002 RAM array is physically and electrically constructed of 20 rows by 16 columns of DRAM cells. The 16 columns are grouped into 4-bit wide "registers". This is much the way it is depicted in the Intel documentation.

This arrangement means all RAM operations -- read, writes, and refreshes -- act on an entire row at a time. The selection of one of the four 4-bit wide registers is handled by multiplexing and not by addressing.

Now let's take a look at what happens in each phase of the execution of an instruction.

The Intel documentation describes the MCS-4 system as having eight non-overlapping phases (A1, A2, A3, M1, M2, X1, X2, X3). Internally, however, there are 16 overlapping phases: A11, A12, A21, A22, and so on to X31 and X32. The screen capture from the Xilinx ISIM simulator makes these phase relationships clearer.

With this in mind we can talk about RAM operations. Let's start with the refresh cycle, which occurs during the M1 and M2 phases when the RAM array is otherwise idle.

1. During the M11 phase, CLK1 causes all column sense lines to be precharged.
2. During the M12 phase, the refresh row counter selects a row to be refreshed. CLK2 causes the selected row to be read onto the column sense lines.
3. During the M22 phase, the selected row is rewritten with the data read during the M12 phase.

The refresh row counter is a 5-bit binary counter. Using the inverted outputs, this counts down from 0x1f to 0x00 and then rolls over to 0x1f again. The upper bit is used to determine whether a "main memory" row or a "status" row is selected. When a "main memory" row is selected, the lower four bits of the refresh counter determine which of the 16 rows used as "main memory" is active. When a "status" row is selected, the lowest two bits determine which of the four "status" rows is active; this causes each of the "status" rows to be refreshed four times while the upper bit of the counter is high.


Now let's look at the RAM array read and write operations which occur during the X1 and X2 phases of instruction execution:

1. During the X11 phase, CLK1 causes all column sense lines to be precharged to a "high" state.
2. During the X12 phase, a row is selected based on the most recent SRC instruction, or the low two bits of OPA for status register read and write instructions. CLK2 causes the selected row to be read onto the column sense lines.
3. During the X21 phase, if the current operation is a read, the data from the selected register is gated onto the data bus.
4. During the X22 phase, if the current operation is a write, the selected row is written. The previously selected register receives the data from the data bus, while the other registers in the row receive the data read during the X12 phase.

One of the things I found interesting about this is that a read operation didn't result in the data being rewritten to the RAM row. Apparently the DRAM cells can tolerate being read twice (once for a read operation and once for the following refresh) without suffering bit-rot.


One of the specified behaviors of the i4002 is that asserting the RESET line for a sufficient period results in resetting all contents to zero. This is done by inhibiting the RAM row read operations. This causes the refresh sequence to write zeros into the RAM, though this requires RESET to be asserted for 32 complete eight-phase cycles. The RESET line also inhibits the data bus multiplexer gate signals, preventing data bus values from being written unintentionally.