Another flaw in the original i4004?

While trying to count the number of latches a signal might need to pass during either the CLK1 or CLK2 pulses, I took a look at a signal named by the analyzer "M12+M22+CLK1~(M11+M21)".  I determined its function is to gate the internal data bus into the scratchpad register array and instruction pointer array, so I tend to refer to this signal as the "data gate". Other signals determine which, if any, of the array cells are written.

This seemed straight-forward enough until I started looking at how this signal is generated. Here's the logic as depicted on the original i4004 schematics:

This circuit can be broken down into three pieces. Moving from right to left we find an inverting push-pull driver. This, in turn, is driven by a three-input NOR gate. The right-most input of this NOR gate is driven by the M22 timing signal, and the middle input is driven by the M12 timing signal. I believe these two terms allow instructions like JCN, JUN, JMS, and ISZ to load the instruction pointer with the contents of the second ROM byte fetched during the M1 and M2 bus cycles. They also support the FIM and FIN instructions which load scratchpad registers with contents loaded from ROM, again fetched during the M1 and M2 bus cycles.

That leaves the logic that drives the left-most input of the NOR gate. The timing circuitry doesn't export the M11 and M21 subcycle signals, so this logic synthesizes them by first NORing together the A32 and M12 subcycle signals and then delaying them using a latch driven by CLK2. This is then ANDed with the CLK1 signal to produce this third term.

I believe this third term supports instructions that perform writes to the instruction pointer (JIN) and scratchpad registers (INC, ISZ, XCH) from sources within the chip, but I haven't verified all the timing yet.

Note, however, that the connection to the A32 timing signal is instead labeled A12 on the original schematic. A connection to A32 is correct to synthesize the M11 term, as described in the naming of the data gate signal, while a connection to A12 would synthesize A21. The data gate signal is written in three different ways on the original schematic, but all refer to M11 rather than A21. This leads me to think this is an error in labeling rather than an erroneous connection.

Here is graph of the various signals generated  by this circuit, along with the CLK1, CLK2, the 8 subcycle timing signals, and the internal power-on clear signal:

The bottom four signals are:

• M12+M22+CLK1~(M11+M21) is the push-pull inverting driver output
• N0708 is the output from the 3-input NOR gate: ~(M12+M22+CLK1~(M11+M21))
• N0278 is the delayed and latched output of the 2-input NOR gate: ~(M11+M21)
• N0279 is the output of the 2-input NOR gate: ~(A32+M12)

The function of N0278 appears to be to block CLK1 from being included in the 3-input NOR gate. But the only time the CLK1 signal is blocked by N0278 is when M12 or M22 are also active, meaning the data gate signal would be active anyway. Thus the exact same result could have been achieved by dropping the M11 and M21 terms, making the equation a much simpler "M12+M22+CLK1". This would have eliminated four transistors and a load.

Why go to all the trouble of synthesizing the M11 and M21 terms and ANDing CLK1 with them when this has no effect on the resulting signal?

I just don't know. Yet.