Thursday, December 2, 2021

Big Verilog source update on OpenCores.org

November 15th, 2021, marked the 50th anniversary of the release of the MCS-4 chipset. I figure this is as good a time as ever to update my MCS-4 project on OpenCores.

 Here's a summary of the changes:

  • Created subdirectories under rtl/verilog for each of the four initial MCS-4 chips. 
  • Moved the i4004 CPU-specific Verilog module files into the i4004 subdirectory.
  • Updated the i4004 CPU Verilog modules with a few bugfixes.
  • Published Verilog modules for the i4001 ROM, i4002 RAM, and i4003 Shift Register chips.

These are the Verilog sources I used in my Busicom 141-PF re-creation using a gutted Canon P170-DH calculator, so I'm pretty sure they work correctly.

Let me know if you find these files useful, or if you find what you think is a bug.

 

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License

2 comments:

  1. Hi, the files obtained from Opencores when downloading the project archive (mcs-4_latest.tar.gz) do not look to be updated. They all show dates of 12/2012 (not 2021). Is there another place where the latest files can be obtained (github, etc.)?

    ReplyDelete
    Replies
    1. It looks like you are correct. The directories in the tarball suggest that it was created in 2019. Unfortunately, I can't force an update of this tarball.

      I have contacted the OpenCores maintainers to alert them to this issue. Until then, you should be able to check out the repository containing the new files using Subversion (SVN):

      $ svn co https://opencores.org/ocsvn/mcs-4/mcs-4

      Delete