Back to the Scratchpad board

i4004 CPU Block Diagram

As I mentioned in the previous post, I've started working on the Scratchpad board again. This is the board that implements the 16 x 4-bit array of internal registers.

Internally, as depicted at the far right side of the i4004 CPU block diagram, this is actually an 8 x 8-bit DRAM array. It's quite similar to the 4 x 12-bit array used in the Instruction Pointer, which I successfully implemented some years ago.

I started laying out this board in August 2012 and last worked on it in March 2016. I'd been hoping to do this work in KiCad v7, but issues with the Eagle schematic importer in KiCad and some other transition concerns have convinced me to complete this project using my perpetually-licensed copy of Eagle v7.7.0.

One of my concerns when implementing the Instruction Pointer board in July 2012 was whether the gate capacitance of the FDV301N MOSFET that forms the DRAM storage element would be sufficient to avoid bit-rot between refresh cycles. In case it wasn't, I added 0604 capacitors in parallel with the FDV301N to the design.

My breadboard experiments in June 2012 suggested these would not be necessary, so when I assembled the IP board I did not populate these capacitors. My tests with this board continue to support this belief, but they've been run with the CPU running at 714 KHz, which is near the upper end of the original chip's operating range of 500 to 741 KHz. Although I have planned to do margin testing of my IP board with lower clock rates, I haven't gotten around to doing so.

The DRAM cell layout I established with the IP board arranges the components on a 0.16 x 0.16 inch grid, which allows the placement of this capacitor in what would otherwise be a blank space. Rather than kick myself later, I've added these capacitors to the Scratchpad board as well.

Here we see the DRAM cell for bit 0 of register 0 (or register 15, I'm not positive which), with the added capacitor highlighted. Note that the layout of the DRAM array is essentially rotated 90° counterclockwise from the schematic:

Most of the work I've done recently has been the tedious and repetitious routing of connections within the 8 x 8 DRAM array. As can be seen above, this cell hasn't been completely routed — it's missing ground connections to the drain of T1443 (lower right) and the substrate of T0474 (lower left).

I'm going to be quite busy for the next couple of weeks with other activities, so I'm thinking it may take until the end of the month to finish routing this board. I'll take a look at the Instruction Decoder and Arithmetic Logic Unit boards, then I'll send this one off to JLCPCB for fabrication. Maybe I'll have it assembled and in the test jig in early July.