Testing the Instruction Pointer board

My project for April and May was to extend my PicoBlaze-based test framework to test the Instruction Pointer board I built in 2012. I also wanted to update the desktop computer in my electronics lab.

I'd completed the Verilog implementation of the i4004 CPU at about the same time I assembled the IP board, so the obvious way to test it was to strip out the parts of the Verilog that implemented the instruction pointer, and let the IP board perform that function. It seemed to work, but later, when I attempted to run the i4004 Clock program on the hybrid setup, it wasn't stable. Sometimes it would run, and sometimes it wouldn't. I wasn't sure why, but I didn't have a way to capture the failure for analysis.

I started with the Scratchpad Register board test program, then recoded the PicoBlaze program to exercise the Instruction Pointer board. I also made a couple of small tweaks to the Verilog to simplify the programming. The intent was to simulate a sequence of unconditional jumps (JUN), subroutine calls (JMS) and returns (BBL), mixed in with instructions that allowed the IP incrementer to do its thing. At the same time, the PicoBlaze program tracked the expected address and compared this with the address captured by the Verilog test framework during the A1/A2/A3 bus subcycles. I tested this against the results generated by the Verilog implementation of the IP function.

The computer in my electronics lab was an old single-core AMD Duron with less than a gig of RAM, running Windows XP. It was a good system for its time, but that time was over 20 years ago. I used it mainly to run the software for my LogicPort logic analyzer, but the latest version of that wouldn't run on it. It was time it was put out to pasture.

I decided to replace the Duron with the computer that had supplanted it in 2015: a dual-core AMD Athlon 64 X2 3800+ CPU. I doubled the RAM from 2 GB to 4 GB, and installed an old 64GB SSD I had laying around as the boot disk and installed Kubuntu 22.04 on it. I reformatted the old 256 GB hard drive to store programs such as ISE, KiCad, Eagle and the like. The biggest issue was the LogicPort software is a Windows program. As it turns out, the LogicPort software runs pretty well under Wine, with the big exception of the USB bus interface needed to talk with the LogicPort pod. I found a project on GitHub called "wineftd2xx" that claimed to provide that missing link, and after experimenting with it for a few days I got it to work. It's a lot slower than my main computer system, but now I can run ISE and LogicPort on the machine sitting on my workbench.

With that set up I tried running the IP test. The way this works is that LogicPort is configured to monitor the interface between my Spartan-3E FPGA board and the Instruction Pointer board. An extra FPGA I/O pin is configured to pulse briefly if the PicoBlaze program detects a mismatch between the address it expects and the address output by the IP board. The LogicPort triggers on this pulse and records the bus activity leading up to that point. I ran the test for over 10 minutes -- more than 50 million instruction cycles -- with nary a single error detected.

Either I need a more rigorous test, or the Instruction Pointer board works as designed.