Incrementer and Column Select

I'm glad I don't do PCB layout for a living -- this is real work! I'm finding I have to be in the right mood, or I end up staring at the components and see no way to route the connections. In the right mood, though, it takes just a few pokes and prods and then everything seems to work without effort.

You may have gotten the idea that I don't use the autorouter very much. I see lots of postings in discussion forums where people throw components on a board, click on "Auto Route", and expect everything to be done for them. Of course, the reason they're posting is the autorouter fails, or produces a tangled mess. I've occasionally given the autorouter a try, just to see what it'll do, but thus far I've never used the results.

This evening I got most of the Incrementer routed. To my surprise the original layout worked pretty well. Ok, I shouldn't be surprised: the real 4004 die and the schematic layouts are almost identical, and my initial layout is based on the same schematic. But I have some constraints the Intel folk didn't.

So here's the board at the end of this evening:

I still haven't placed the carry circuits, but that's next.

I placed the Column Select logic in the lower left of the board. This will drive the 3:1 muxes I placed earlier through the horizontal traces below the mux transistors. These traces appear blue in the screenshot because they're on the back side of the board. The Column Read Select circuits on the right edge of that group are routed, but I haven't started routing the Column Write Select circuits yet.

I also sketched in the group traces that form a sort of central bus in the 4004. The two external clock lines and all 8 of the phase enable lines are represented here. They appear as a hatched red in the screenshot because they're placed on layer 3, one of the two inner layers of the 4-layer board. My plan is to keep layer 2 as a solid ground plane (solid except for the thermals around the vias). When layers 1 (top) and 16 (bottom) aren't enough, I'll steal from the Vdd plane on layer 3.

I did a quick count, and there are 57 transistors and 21 resistors yet to be placed. Most of these are from the Row Select logic. I'm hoping that'll fit in the remaining area at the lower right of the board, otherwise I'll have to rearrange the Column Select logic to be higher and narrower. A quick count of layout grid squares says there is a 6 x 20 area free, but as with the Column Select logic, the structure doesn't necessarily lend itself to tight packing.