Margin testing detail

Here's a schematic of the worst-case margin test circuit:

In all cases the substrate pins are pulled to ground. Here's a brief overview of the circuit:

• CLK1 and CLK2 are two non-overlapping, positive-going, pulses. I used a PIC to generate the two clocks.
• Q1/R1 serve to isolate the output of the PIC from the varying VDD of the test circuit. It also converts the PIC's push-pull output to something more characteristic of the signals generated by the resistive pull-up design of the i4004.
• Q2/R2, Q3, and Q4 form the push-pull output circuit commonly used in the i4004 to drive high-capacitance circuits. R2 would normally be "bootstrap load".
• Q5 is used as a "transmission gate" or "pass gate". This is the one situation where a four-terminal MOSFET like the BSS83 is critical, as the substrate must be kept at a lower voltage than the channel or the body diode will conduct. The input to Q5 would normally be a logic signal, but for this test it's strapped high.
• Q6/R3 form a simple inverter to allow measurement of the threshold voltage of a BSS83 in grounded-source mode.
• Q7 discharges the gate of Q6 to allow observation of the turn-on characteristics of Q5.

The circuit operation is as follows:

1. With CLK1 low Q1 is off, allowing R1 to turn on Q2 and Q4; Q2 thus turns off Q3. With Q3 off and Q4 on, the gate of Q5 is pulled to ground, closing the transmission gate and preventing input changes from affecting Q6. Q6's gate floats, holding whatever value it previously had.
2. When CLK1 goes high, Q1 turns on. This turns off Q2 and Q4; R2 thus turns on Q3. With Q3 on and Q4 off, the gate of Q5 is pulled to VDD less the Vgs(th) drop across Q3. The input signal to Q5 (VDD, in this case) is passed to the gate of Q6; if this level is sufficient to turn on Q6, OUT will go low.
3. When CLK1 goes low again, Q5 will turn off. The capacitance of the gate of Q6 and the circuit driving it will hold whatever level was present on the input of Q5.
4. When CLK2 goes high it turns on Q7, discharging the gate circuit of Q6 and causing OUT to go high.

With the PIC alternately pulsing CLK1 and CLK2, OUT should toggle cleanly. If OUT does not pull to ground cleanly and rapidly, the circuit has failed.

My first series of tests were performed with the circuit as shown. Here's a table of the results:

VDD	Q5 Vg	Q5 Vs	Q5 Vgs
7.0V	5.6V	4.2V	1.39V
6.0V	4.6V	3.3V	1.33V
5.0V	3.7V	2.4V	1.30V
4.0V	2.7V	1.6V	1.19V
3.5V	2.5V	1.4V	1.17V

At VDD of 3.0V, the Q5 Vs (which is also the Q6 Vg) was below the level sufficient to turn on Q6. This is the failure criteria.

My second series of tests were performed with two modifications to this circuit: Q3 was replaced with a DMN26D0UT and Q4 was replaced with an FDV301. Here's a table of the results:

VDD	Q5 Vg	Q5 Vs	Q5 Vgs
7.0V	6.4V	4.9V	1.48V
6.0V	5.4V	4.0V	1.44V
5.0V	4.4V	3.1V	1.33V
4.0V	3.4V	2.1V	1.26V
3.5V	2.9V	1.65V	1.24V
3.0V	2.4V	1.25V	1.21V

At VDD of 3.0V, the Q5 Vs was just high enough to turn on Q6, albeit slowly; a very small VDD decrease resulted in failure. It's pretty clear that using a DMN26 for the high-side driver boosts the push-pull "high" output by about 0.7V, which translates to similar increase in a pass-through voltage.