Puzzling out the Bootstrap Load

One of the sub-circuits in the 4004 that has always confused me was the so-called "bootstrap load". It's depicted in the schematic as a resistor with a "B" next to it, but the legend gives more detail. Remember here that I'm a software engineer and have no formal training in electrical engineering, let alone materials science.

i4004 Schematic Legend

Researching the construction of integrated circuits reveals that true passive resistors can take up a significant amount of silicon area, while transistors are usually smaller. By careful design of the transistor, it's possible to create a small transistor that acts pretty much like a passive resistor. Thus the legend indicates that what is shown on the schematic as a pull-up (or "load") resistor is really a single MOSFET with its gate and drain connected to VDD.

However, the "bootstrap load" circuit shown at the bottom is more complicated. It consists of two MOSFETs and a capacitor. How does this thing work? I made the assumption that bootstrap load was used when a faster rise-time was needed, but I really didn't understand how this circuit worked.


At first I thought it might be some sort of constant-current circuit. I looked at constant-current circuit designs using FETs but none of them seemed to match. I tried bread-boarding the circuit, first with enhancement-mode FETs, then with depletion-mode FETs, but neither produced any useful results. And what was the capacitor for? Eventually I decided I simply didn't have access to the correct sort of transistors. A chip designer can easily customize the characteristics of each transistor to the job, but I'm limited to commercially-available types.

Not being constrained by the limits of silicon area or power dissipation the designers of the 4004 faced, I chose to use lower-value resistors (2.2K vs 4.7K Ohms) in place of the original bootstrap load circuits. That seems to work just fine for the Instruction Pointer board, but didn't help me understand how the bootstrap load circuit works or why it was needed.

Federico Faggin's article on the development of Silicon Gate Technology contains this explanation of the bootstrap load:

One of the crucial circuits that needed a capacitor was the so-called bootstrap load. A bootstrap load allows a logic gate to achieve an output swing equal to the supply voltage, Vdd, rather than (Vdd – Vt), which is the output voltage produced by a conventional MOS transistor load with threshold voltage Vt. When this output voltage is applied to the gate of a pass transistor, i.e. a transistor that is in series with the gate of another transistor, the signal out of the pass transistor is one additional threshold voltage drop below (Vdd – Vt), and this new signal is generally not sufficient, in the worst-case condition, to turn on the transistor driven by the pass transistor. (In this analysis one needs to remember the existence of the so-called body-effect, whereby the threshold voltage of a transistor whose source is at a different potential with respect to the substrate, is augmented by an amount proportional to the square root of the source-to-substrate voltage. The threshold voltage increase due to the body-effect can be significant, and this is the case for both an MOS transistor load and a pass transistor).  

So now we know why the bootstrap load was needed; it's not speed, it's voltage margins. But how does it work? At some point it occurred to me that this was similar to the bootstrap circuits used to drive high-side power MOSFETs. The problem everyone is trying to solve is to be able to drive the gate of a FET to a voltage above that of the source, while minimizing the voltage drop across the FET when it's turned on.  To achieve this, the gate must be driven to a voltage above that of the FET's drain. How do you do that cheaply? The trick is to connect one side of a capacitor to the FET's source, and the other side to a positive voltage source (such as Vdd) through a diode. When the source is pulled to (or near) ground by the low-side driver, the capacitor charges through the diode. When the low-side driver turns off, the capacitor holds a charge which is sufficient to drive the gate above Vgs(on) regardless of Vds. Want pictures and a better explanation? Check out this appnote (PDF) from Silicon Labs.

Let's go back to the bootstrap load circuit. First, assume both FETs are intrinsically designed to act like resistors when their gates are connected to their drains. Then recognize that the upper FET will act like a diode if the source rises above its gate, which is tied to Vdd. Now the operation of the bootstrap load circuit makes sense:

1. When an external circuit pulls the source of the lower FET to ground, the capacitor charges through the upper FET, which acts as a diode. As the gate of the lower transistor rises to Vdd it partially turns on, acting as a resistor (this is wasted energy, but can't be helped).
2. When the external circuit stops pulling the source of the lower FET to ground, it rises toward Vdd. The capacitor holds its charge, maintaining the lower FET's Vgs and keeping it turned on. The upper FET turns off, preventing the lower FET's gate from discharging to Vdd.

This works around the intrinsic problem with enhancement-mode FETs: once Vgs drops below the threshold voltage it turns off, limiting the maximum output voltage to Vdd - Vgs[th]. This is a big deal when the gate threshold voltage is around 3.7V, which is 25% of the 15V operating voltage.

My choice of load resistors for the Instruction Pointer board was entirely arbitrary, as was my choice of 4.7K resistors for normal loads; all my breadboard work was with 10K loads (mainly because I have a bag of several hundred on hand) and that seemed to work quite well. The only reason I switched to 4.7K because I was unable to get decent simulations and I didn't want to do the rigorous analysis necessary to choose optimal values, and was concerned it wouldn't work. There are 361 normal loads and 66 bootstrap loads in the 4004; if all are pulled to ground simultanously they'll draw only 534 mA and dissipate 2.67 W. Realistically I doubt if half are active at any time.

Now that I understand the operation of the bootstrap load I may take another look at the rest of my implementation. My load resistors will pull all the way to Vdd eventually, and the gate capacitances of my transistors are quite low (10pF for the FDV301, 1.6pF for the BSS83). Four of the seven uses of bootstrap loads on the IP boards drive about 25pF, suggesting a rise time to 4.5V of about 126ns. It'd be interesting to stick my scope (and another 10pF) on these points and see what the rise time actually is, and what effect it has on the signals passing through the pass transistors.