Eagle track length calculation errors

I decided to see if I could simulate the CLK1 and CLK2 signals on my current Instruction Pointer board using LTspice. Why these two? They're the only signals that have rapid rise times, as the others are all limited by the RC rise time curves of the pull-up resistors and the gate and drain capacitances they drive. To do this with any accuracy I needed to simulate the actual track lengths and capacitances at their ends.

When I was an undergraduate university student, we used to get students from other majors wandering into the computer lab inquiring about the then-new and exciting computer science degrees. Many of them correctly perceived that this was going to be an in-demand and potentially lucrative field, but most had absolutely no idea what was involved. One of the screening questions I asked was this:

Let's say you have a repetitious task to do that takes you 30 minutes to do, but you have to do it every week. Alternatively, you could write a program to have a computer to do that task, but it'll take you 8 hours to write the program. Which would you do: 30 minutes every week, or 8 hours and be done with it forever?

Most people answered, "I'd spend 30 minutes a week; it's not worth 8 hours to automate it." I would point these people to the door and wish them luck in their current majors. Those who answered, "It sounds like fun to make the computer do it, and I'd never have to do it again" I would invite to inquire further. They were the sort of people who would make good software engineers.

As proof of this, I found myself writing a program to analyze the XML file Eagle uses to store its representation of a PC board layout. When finished I'll be able to tell this program to describe the tracks leading from a specified pad (for example, the inter-board connector pin A19 that carries CLK1) and it will report track lengths, widths, and terminating devices all ready for input to Spice. I spent all day Sunday on it, and it's not quite done. Since I'm really only interested in two signals I probably could have made a spreadsheet of all of this data segment-by-segment and been done with it. But I wouldn't have had as much fun doing it.

Eagle has a ULP (User Language Program) that reports the total length of specified signals, but it doesn't distinguish between a simple point-to-point track that could be represented by a single Spice "tline" model and a complex series of branches that would require multiple tlines. But it made a useful reference to check the results my program generated as development progressed.

However, it became increasingly obvious that my program reported subtly different results. In every case, my program reports longer total length than the Eagle ULP. Both couldn't be right, so which program was in error?

Eventually I determined the source of the discrepancy. The Eagle ULP does not account for the length of vias connecting one board layer to another. While this may sound like insignificant, every via connecting the top layer to the bottom layer adds the thickness of the board, or 1.6 mm (0.062 inches). On my CLK1 signal with 8 vias, this accounts for a 12.8 mm (0.5 inch) difference. That is not an insignificant length when performing a simulation.

I'd report this to the folk at CadSoft, but CadSoft no longer exists and I have no particular desire to help Autodesk.