Scoping the CCLK line

Given how much time I spent fretting over the layout of the configuration clock (CCLK) circuit (1, 2, 3, 4), it seemed strange that I hadn't gone back and checked what the signal actually looked like on the board.

First I decided that I should find out whether the full Busicom 141-PF emulation would load from Flash ROM. I build a ROM image of the FPGA bit file and programmed the ROM, only to be somewhat distressed that the Xilinx tools reported the DONE line had not gone high as it should have. However, after a power cycle, the FPGA DONE line did indeed go high, and the calculator seemed to perform properly. It's something to look at later.

Then I took the board down to my electronics lab and fired up my oscilloscope. Although the frequency of the CCLK circuit isn't high (roughly 1 MHz to start), it is very sensitive to reflections and other noise. To minimize loading the circuit with the 'scope probe I used my 1 GHz active probe for the first time.

As it turned out, there really isn't anything interesting to see:

Seriously, that's about as clean a clock signal as you can ask for. I even looked at this signal with a much higher sweep rate and it doesn't show much more. I guess I shouldn't be too surprised, but it's still a relief.