Semi-final CCLK layout

Here's a screenshot of the current, and potentially final, layout of the FPGA configuration clock line (CCLK in the Xilinx docs, labeled CFG_SCK on my schematic and board).

The TQFP-144 footprint in the upper left corner is U1, the Spartan 6 FPGA. The WSON-8 footprint in the lower center (with the big "9" on its heatsink pad) is U2, the S25FL128L Flash ROM. For scale, U1's pads are on 0.5mm centers, while U2's pads are on 1.27mm centers.

The CFG_SCK track is 0.3mm wide, giving it a characteristic impedance of 50 ohms.

The two large resistors near the lower left corner of U2 form the Thevenin terminator, should it be needed. They are 0603 packages due to their dissipation of 109mW when the CCLK output is driven to either rail (Vcco_2 is 3.3V). The other components around U2 are 0402 packages, including the pads for the 0 ohm jumper.

Xilinx UG380 Figure 2-22

The reason I've chosen this layout is that without the jumper in place there is a minimum of disruption of the track between the FPGA and the Flash ROM. With any luck this is how it'll stay. With the jumper in place it bears a passing resemblance to the specified layout with a short 2mm stub to the ROM in the middle and the terminator at the end.