CCLK Terminator Three

After much debate and vacillation, I've decided how I'm going to handle the CCLK circuit termination.

For detailed background, read my posts The CCLK Terminator and Terminator Two.

In summary, the SPI clock output from the Spartan 6 to the Flash ROM holding the FPGA's configuration file is extremely sensitive to double-clocking due to reflections and poor signal integrity. To avoid such problems, Xilinx devoted three pages of their configuration user guide (UG380) to the board layout of this one signal.

The problem I've been wrestling with is that their recommended solution consumes a lot of power even when the Flash ROM is not being accessed. I've considered many possible solutions (and learned a lot about signal integrity, IBIS models, and circuit simulation with Spice). The termination options I've seriously considered are:

1. Thevenin termination: A pair of resistors, one to Vcc and one to GND, the equivalent impedance matching that of the transmission line. This consumes 55 mW when idle, and when driven either high or low to take the pin out of digital "no man's land" that goes up to 110 mW. This is the Xilinx-recommended solution.
2. Parallel termination: A single resistor to ground, matching the impedance of the transmission line. This consumes a lot of power when active, but nothing when idle.
3. AC termination: This is a variant of parallel termination, but uses a small capacitor in series with the termination resistor to eliminate DC current flow. This reduces the power required when active and requires no power when idle. However, there can be offset issues when the clock first starts, and finding the correct capacitor value is reportedly tricky.
4. Source termination: A resistor in series at the source raises the driver output impedance to match the transmission line. This draws the least power when active and none when idle. Unlike the previous options, it results in reflections returning to the driver; however, these reflections may occur at voltage levels that are not significant to digital inputs.
5. Lumped Circuit: This option places the components closely enough that they appear as a lumped circuit rather than a driver and receiver separated by a transmission line delay.

I quickly decided against AC termination (Option 3) because the active period for this signal is quite short, giving no advantage over parallel termination (Option 2). Initially I thought parallel termination (Option 2) wasn't feasible at all because CCLK is configured as an 8 mA output, and at 3.3V a 50 Ohm terminator requires 66 mA to reach full voltage swing. The IBIS characteristics suggest this might work, though it's not clear.

Thus when I created the schematic I went for both options 1 and 4, with provisions for both a series resistor and Thevenin pull-up/pull-down resistors. However, the series resistor means a transition from a 50-ohm transmission line to the source termination resistor and back. To create a 50-ohm transmission line on the two four-layer board stack-ups offered by JLCPCB require either a 12 mil or 6 mil wide trace. The pad for a 0402 resistor is 24 mils wide, which will result in impedance discontinuities. Would this be significant enough to cause a problem? I don't know, and I don't have access to tools like Hyperlynx (or, more properly, I'm not willing to spend $299 for 3 months access to it). So I've removed the series termination resistor pads.

My simplistic simulations with Spice suggest that if I keep the length of the CCLK track to about an inch or less, it looks like a lumped circuit and reflections shouldn't be an issue. I've decided to lay out this circuit for Thevenin termination (Option 1), but I won't install the termination resistors at first. If it works reliably without termination I'm done. If not, I can add one or both resistors for parallel or Thevenin termination.