I found a lingering transparent latch in the implementation of the Instruction Decoder module, and I replaced it with a clocked flip-flop. I did a double-check of the Verilog sources, and I think that's the last one.
The OpenCores repository has been updated.
Speaking of OpenCores... When I went to update my project, I discovered the site's encryption certificate has expired. And I still haven't gotten a reply to my report of the out-of-date download tarball. I'm not getting a good feeling about the future of the site.
Maybe someone should archive the site?
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