Poor Prior Planning Problems

Having received my new Scratch Pad Register boards from JLCPCB, I collected the parts I needed to populate the board. Everything was going well until I opened the container of solder paste: it was completely hard and dried out. I really should have anticipated this, since the last time I used it was three years ago. *sigh*

A new container of solder paste is only $14, and this should enough for me to finish the remaining four boards in this project. However, because of its weight, the shipping costs another $7. Rather rush to place an order and pay 50% in shipping, I spent a day looking at all the projects I'm working on and made a list of things I needed for them. I placed a combined order with DigiKey early Monday morning, for no increase in shipping cost. It arrived this afternoon.

Rather than try to populate and reflow the entire board in one evening — over 500 surface-mount components — I decided to do only the right 1/3rd of the board. This includes the control decode logic and refresh counters, but excludes DRAM array and its drivers. This took about 2.5 hours. Curiously, I found the slowest component to place to be the resistors, as they have to be flipped over so the marking is on top, and then rotated because I'm obsessive enough to want them all to read from the same angle. The 4-lead BSS83Ns were the next slowest, because it took extra effort to confirm their orientation. The 3-lead FDV301s were the fastest to place — about 10 seconds each — as their orientation is obvious.

All this his suggests the rest of the board will take another 5 hours to assemble. Then I need to wire the additional six circuits this board requires through level shifters on my debug board so the FPGA can drive them. After that, I'll switch gears and generate a Verilog top module that uses of the Scratch Pad Register board instead of the Verilog module it currently uses.

Initially, I think I'm going to test this board alone, rather than with the Instruction Pointer board. Once that seems to work reliably I'll plug both boards into the debug board, rework the Verilog test module yet again, and test the two board together.

Because of how many signals pass between the Instruction Decode and Arithmetic Logic Unit boards, they'll need to be tested as a pair. I simply don't have enough I/Os from the FPGA board to test either of these separately. That means finishing the layout of both boards and sending both out to be fabricated. I probably won't get that done for another couple of months. Hand-assembling them will take several days, as there are almost 800 components between the two.