Scratchpad Register board ordered

After starting the layout of the Scratchpad Register board in August 2012 — yes, 11 years ago — it has finally been sent out for fabrication by JLCPCB in China. Here's what they say it will look like:

 

If they keep to schedule, production should start Monday (China time) and take 3-4 days. This would have the boards and stencil ship Friday-ish. I opted for the default DHL Express (2-4 day) shipping so they should arrive sometime the following week.

The biggest change in the last two days is the addition of four 33µF tantalum capacitors on the corners, and eleven 100nF ceramic capacitors along the top and bottom edges and down the middle. These capacitors are connected between the VDD and GND planes, and serve to dampen any transients caused by state changes.

Most other changes are cosmetic. I outlined each of the subcircuits in the silkscreening, and annotated each with the function the subcircuit performs. I did this on the Instruction Pointer board, and found this makes it easier to probe the circuits with an oscilloscope. It also helps explain how the board functions to those who foolishly show interest in my insanity.

One place this annotation is especially helpful is identifying which DRAM cell represents which bit in which register. 

First, here's the structure of the array according to Table III of the 1973 MCS-4 User's Manual:

Looking at the board's DRAM array layout, which follows the layout in the actual chip, it appears to follow the same structure: an 8 x 8 array of DRAM cells, each row representing the eight bits of a pair of four-bit registers. However, while each row does represent a register pair, the layout of the bits is not as shown in the table. Instead, the left-most two columns represent Bit 0 of both registers in a pair, the next two columns represent Bit 1 in a pair, and so on. I'm sure this is for routing simplicity, as it places the multiplexer for each bit below the two bits it muxes. 

What's odd, though, is that the order of the two bits reverses for each pair of columns. For Bit 0, the odd register bit is the column on the left and the even register bit is the column on the right. For Bit 1 these reverse; the even register bit is the left column and the odd register bit is the right column. Bit 2 has the same arrangement as Bit 0, while Bit 3 matches Bit 1. Having this sort of oddity identified on the silkscreen will avoid me having to remember such trivia should I need to hunt down a problem.

I'm assuming this had something to do with routing of signals in the chip, but that's only a guess at this point. It might be interesting to look at the metal layers in the chip to see if the reason is clearer.