Instruction Decoder assembly

My JLCPCB order containing both the Arithmetic Logic Unit and Instruction Decoder boards arrived Thursday afternoon, nine days after I submitted the Gerber files. As is their practice, each stack of five boards are shrink-wrapped together so the boards can't shift against each other and cause damage.

ALU and ID boards sent for fabrication

I started laying out the Instruction Decoder board in late November 2012, and started the Arithmetic Logic Unit board ten days later. Now, only 147 months later, I finally finished their layout and sent them off to JLCPCB for fabrication. Woo hoo!

Fabrication time is quoted as 5-6 days, and shipping from China adds another 2-4 days. That puts delivery in the first week of April. That'll give me time to do my taxes without this as a distraction.

Arithmetic Logic Unit board fully routed

 Here's the Arithmetic Logic Unit board:

All nets have been routed, and the design rule checks run without error. 

Instruction Decoder board layout complete

 Here it is, the (hopefully) final layout of the Instruction Decoder board:

Like the previous two and several to follow, this board uses stacking connectors to make the connections between it and the other boards that make up the i4004 CPU. Initially I thought all the inter-board connections could be made through the connector on the right, but once I'd split the master schematic into five smaller schematics I realized that this board and the Arithmetic Logic Unit board had so many connections that a second connector was needed. Thus the connector on the left was added to the designs.

I thought I was done with this board a few days ago, but while checking the connector pinouts against my master spreadsheet of interboard connections I realized there were six that didn't have pin assignments. These nets were fully routed within the board, but didn't connect to pins on a connector. This would have been something easily correctable by adding wires to the board later, but of course it's better to have caught it now.

There are a few reasons I'm I haven't sent this board to JLCPCB for fabrication. The primary reason is that I can't test this board without the ALU board; my FPGA interface board just doesn't have enough I/Os to be able to connect to all the ID board outputs. So there's little benefit to sending this one out without the ALU. Secondly, the shipping cost for this board alone is the same as for this board and the ALU board together, and ordering them together will save me about $25.

The only change I might make to this board before ordering is to reduce the layer count from 6 to 4 by merging the interior signal layer into the power distribution layer. The cost difference is only $6, but with resistive pull-ups I don't need a full power plane and it annoys me to have the extra layers.

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What about the ALU board? There are still 60 unrouted nets remaining. A portion of the circuitry is incompletely routed, and I'm not happy with the component arrangement in that portion. I'm thinking it'll probably be sometime next week before it's finished.

JLCPCB design rules for Eagle

A couple of days ago I "finished" routing the Instruction Decoder board. To be sure JLCPCB wouldn't have manufacturing problems, I used the same Eagle design rules file (DRU) I'd used to fabricate the Scratchpad Register board.

The Scratchpad board's DRU file started with the Eagle DRU file JLCPCB posted on GitHub for use with 2-layer boards which I modified for the 4-layer stack-up. Since JLCPCB's published capabilities allow tighter spacing on 4- and 6-layer boards I assumed this would be safe. The Scratchpad board works, but was this a good assumption?

The Instruction Decoder PCB

When I started my efforts to construct a discrete-component replica of an Intel 4004 CPU in June of 2012, I realized that I was going to have to split the CPU into several parts. This was largely dictated my hobbyist license for the Eagle CAD program, which limited me to placing components within a 160mm x 100mm rectangle (that's 6.3 x 3.9 inches). So I split the CPU into five boards:

• Instruction Pointers
• Scratchpad Registers
• Instruction Decoder
  
• Arithmetic/Logic Unit
• Timing and Input/Output

By October 2012 I'd assembled a working Instruction Pointer (IP) board, and tested it using an FPGA to substitute for the remainder of the CPU.

Scratchpad Register board delivered

This afternoon a DHL courier dropped a package at my doorstep. JLCPCB shipped it with a signature release required, but I waived the signature in advance.

I'm old enough to remember when placing a domestic mail order came with an "Allow 6 to 8 weeks for processing and shipping" disclaimer. Yet I sent this order to China electronically only 10 days ago. A week ago this physical package was in China, and now I'm holding printed circuit boards.

Scratchpad Register board ordered

After starting the layout of the Scratchpad Register board in August 2012 — yes, 11 years ago — it has finally been sent out for fabrication by JLCPCB in China. Here's what they say it will look like:

 

If they keep to schedule, production should start Monday (China time) and take 3-4 days. This would have the boards and stencil ship Friday-ish. I opted for the default DHL Express (2-4 day) shipping so they should arrive sometime the following week.

Thank you, FedEx!

I received my 4-layer printed circuit boards from JLCPCB today as scheduled. I put one on my bench and ran some basic checks with an ohmmeter, checking to make sure none of the power buses were shorted to ground or each other, and that they connect to the most remote devices on the board. They look great and I didn't find any electrical issues.

The solder stencil came in the same box, enclosed in a separate plastic sleeve which protects it from damage. It, too, looks great, and I very much like the protective sleeve.

I also got the notice of refund from PayPal for the scratched board: $12.66. Thank you, JLCPCB. I'm going to add them to my list of preferred vendors.

Finally, thank you DHL for delivering on schedule, even though it's a week before Christmas and I'm sure you're dealing with higher than normal volumes.

Wait... DHL? What about FedEx?

Scratched

I received an email from JLCPCB shortly after 3am this morning (4pm Monday in China) indicating they had a problem with one of the boards I ordered:

Thank you for your order from JLCPCB. Your order is completed now, but we regret to tell you that there is is 1 pcs less due to the scratch during the manufacturing process.

To not delay the delivery of your order, we sent those PCBs that are good out first. For the remaining quantity, we can remake and resend or refund the cost accordingly. Please kindly let us know which you prefer.

So sorry for the inconvenience caused!

Nudge... nudge...

I've been eagerly watching the progress of my PCB through JLCPCB's production process. Or not progress, I should say.

I submitted the files Monday morning (US), which would be in the wee hours of Tuesday morning in China. When I next checked the order's status I saw that it had completed the first step of production, "MI", which appears to involve checks of the submitted Gerber files and identification of plated-through holes. With this complete I expected my order to progress rapidly, as had my previous order for the 2-layer fit-test board. But it hadn't.

A day late and...

I finished routing and cleaning up the "final" four-layer replacement PCB for the Canon P170-DH calculator late last night. I didn't trust myself to submit the job properly at 2am. With the 13 hour time difference to Hong Kong it was already late Monday afternoon there, so I went to bed.

The Fit-Test board has paid for itself

The fit-test board I had fabricated has paid for itself!

This is the footprint for a TI TPD4F003 four-channel EMI filter with ESD protection. There are two on this board. This one protects the JTAG interface and the other protects the External I/O interface. It's a tiny little device, measuring only 1.80mm x 1.45mm, with pads on 0.40mm centers. For comparison, the pads on the JTAG connector visible in the lower right corner are on 2.00mm centers.

It's a little hard to tell because of the glare in this photo, but while the large rectangular ground pad in the middle is exposed, the four signal pads on each side are covered with solder mask. This would cause me serious trouble, as I'd have to try to scrape the solder mask off the copper pads before soldering the part in place without causing too much damage to the pads that are only 0.25mm wide. Even then I'd be soldering to bare copper rather than prepped with ENIG.

Lessons from the Fit-Test board

I learned several things from the fit-test board, the most important of which is how to create a KiCad footprint with an NPTH (non-plated through hole). Unlike Eagle, which I recall has a "hole" tool, holes in KiCad footprints are specified by instantiating a "Pad" with a hole of the desired dimension, and setting the pad type to NPTH.

However, that isn't sufficient. You also need to change the pad size to match the hole size, otherwise the hole will have a copper annular ring of the default diameter (1.3mm diameter around my 1.0mm hole). Board houses (JLCPCB and OshPark, at least) seem to interpret this as a plated-through hole. It's also reportedly a good idea to untick the boxes for "technical layers" like solder mask.

Replacement PCB test-fit, Part 2

My 2-layer fit-test boards arrived today from JLCPCB in China. They were shipped in a sturdy box which fit the boards quite nicely, with sufficient bubble-wrap padding to keep them from rattling around inside the box. The boards themselves were vacuum-packed in yet more bubble-wrap so they didn't rub against the box, the outer bubble-wrap, or each other.

A cursory visual inspection didn't show any serious flaws. The worst I noted was some fine-line silkscreening had some small gaps. I'll probably fatten up the line widths to avoid this. I made no effort to move the part reference designations from where they landed when I originally placed the parts, so a lot of it is a jumbled mess or would overlap component pads, but all of it is sharp and easily readable with no apparent blobs or gaps. I'll put the boards under a microscope another time to check the pad shapes and such, but it looks pretty good under a simple magnifying lens.

Now to the three big questions:

• How well does the board fit in the P170-DH calculator shell?
• How well do the keypad contacts work?
• How well do the slide switch contacts work?

Fit-test board fabrication progress

In addition to checking that I have the mechanical dimensions correct on my replacement PCB for the Canon P170-DH calculator, the fit-test board serves another purpose. This is the first time I've ordered a board from JLCPCB, a large Chinese fabrication house based in Hong Kong. This will give me a chance to look at the quality of their work and get a feel for the process and timing of their system.

Measure 17 times, fabricate twice

I've been trying to finish the routing on this board, but keep thinking "what if the holes need to be moved? So I decided to send off my current layout as a 2-layer board for fabrication. Since it's missing the inner two layers there are lots of vias that go nowhere, so I specified that it should not be electrically tested.

I decided to splurge and order it with the ENIG finish rather than HASL, even though it would more than double the cost of the board from $14 to $33. I want to try out the keypad and sliding switch contact patterns laid out on the back side of the board, and the only way I'll get a reasonable test is with the ENIG finish.

To facilitate this testing I decided to generate Gerber files with the vias un-tented. This means that there won't be solder mask over the vias, making them easier to access for testing. I should be able to hold ohmmeter probes in the via holes, or tack-solder wires to the vias.

If all goes well I should have the fit-test board in hand in a week or 10 days.