ALU and ID boards sent for fabrication

I started laying out the Instruction Decoder board in late November 2012, and started the Arithmetic Logic Unit board ten days later. Now, only 147 months later, I finally finished their layout and sent them off to JLCPCB for fabrication. Woo hoo!

Fabrication time is quoted as 5-6 days, and shipping from China adds another 2-4 days. That puts delivery in the first week of April. That'll give me time to do my taxes without this as a distraction.

Although the Instruction Pointer and Scratchpad Register boards have the highest number of components, a large portion ended up in a nice rectangular array. As a result I was able to route these boards using only four layers. Using Eagle's numbering (in which the bottom is always layer 16), here's the stackup for the IP and SP boards:

• Layer 1: All SMT components, long north-south tracks, local connections where possible.
• Layer 2: A solid ground plane.
• Layer 15: A solid power plane
• Layer 16: Long east-west tracks, local connections where necessary.
  

Once I got the components placed on the ALU and ID boards it became apparent that trying to route this on two routing layers was going to be a real pain. For the longest time my plan was to lay them out as six-layer boards, and if I'd only used one inner layer for routing I'd merge it into what had been the solid power plane in the previous boards. As an experiment I tried doing the merge to see what it looked like. I ended up with one disconnected island that could easily be fixed by rerouting one track, but I always closed the layout without saving it.

Two factors weighed against doing this. The primary factor was the tiny increase in cost of a 6-layer board over a 4-layer board: $6 for the minimum order of 5 boards, and an extra day or two lead time. The other factor was the loss of a nearby plane for return currents.

The FDV301N MOSFET was designed as a digital switch, not an amplifier. In my application, when it turns on it turns on fast. This 'scope capture shows T0430 pulling its drain from +5V to ground in less than 5 ns. That's much faster than the 30 ns I expected. (This was captured with a LeCroy DDA-120 digital oscilloscope and an AP020 1GHz active FET probe with a 1.8 pF input capacitance. So, yes, it's legitimate.)

The default JLCPCB 6-layer stackup results in very narrow separation (about 0.1 mm) between layers 1-2, 3-14, & 15-16, while the spacing between layers 2-3 and 14-15 is much greater (about 0.55 mm). Since all rigid PCBs are manufactured with an even number of layers, I settled on this stackup:

• Layer 1: All SMT components, local connections where possible.
• Layer 2: A solid ground plane.
• Layer 3: A solid power plane
• Layer 14: Long north-south tracks
• Layer 15: A solid ground plane
• Layer 16: Long east-west tracks, local connections where necessary.

This keeps all the routing layers close to a solid plane, though admittedly my power plane isn't ideal for this. I do have some small ceramic bypass capacitors scattered around the board in addition to four tantalum bulk capacitors at the corners, but I'm sure the placement is less than ideal.

Realistically, this is all overkill. I don't have to pass FCC testing for EMI, and the circuitry is level sensitive rather than edge sensitive. Still, it's good practice and spending $12 more for a pair of 6-layer designs isn't going to make me go hungry.