The Instruction Decoder PCB

When I started my efforts to construct a discrete-component replica of an Intel 4004 CPU in June of 2012, I realized that I was going to have to split the CPU into several parts. This was largely dictated my hobbyist license for the Eagle CAD program, which limited me to placing components within a 160mm x 100mm rectangle (that's 6.3 x 3.9 inches). So I split the CPU into five boards:

• Instruction Pointers
• Scratchpad Registers
• Instruction Decoder
  
• Arithmetic/Logic Unit
• Timing and Input/Output

By October 2012 I'd assembled a working Instruction Pointer (IP) board, and tested it using an FPGA to substitute for the remainder of the CPU.

The PCB for the IP board was fabricated by Beta LAYOUT GmbH in Germany using their PCB-Pool service. Including shipping, the bare 4-layer PCB with an ENIG (electroless nickel, immersion gold) finish and a single solder stencil cost me just under $200.

Over the next few months I began laying out the other four PCBs. Due to a combination of real life, work, and other hobby projects, progress on the other boards came to a halt in March of 2016.

In April of last year I decided it was time to restart work on this project. I finished the layout of the Scratchpad Register PCB in early September and sent it off to JLCPCB for fabrication. This board is identical in size and construction as the IP board, but cost about half what the IP board cost. I also received five of them for that price, though I have no use for the extras.

I assembled the SP in late September. During the fall I developed and ran some rather in-depth tests of this board, and mated it to the IP board for additional testing.

Now I've begun finishing the layout of the Instruction Decoder board I started in 2012. Although this board has a fewer components than either the IP or SP boards it's more complicated to route. Large portions of the IP and SP boards are taken up by the rectangular DRAM arrays, which have a simple grid of connections. As a result, in 2016 I'd changed the board from 4 to 6 layers, even though that would (at the time) result in a significant increase in the cost of the board. 

I'm now down to the last 30 airwires (unrouted segments), and none of these pose a challenge. If I could test this board separately I'd ship it off for fabrication next week. Unfortunately, due to limitations in my test jig, I can only test it when mated to the ALU board, and that board isn't fully routed yet either.

Both the IP and SP boards have a full-sized copper planes the inner layers: ground on layer 2, and power on layer 15 (Eagle numbering). All other signals are routed on the outer two layers (1 and 16 in Eagle numbering). The current 6-layer stackups for the ID and ALU boards keep the power and ground planes as they are, but add two copper layers between the planes (3 and 14 in Eagle numbering) for routing signals.

Six-layer boards are more expensive than 4-layer boards, but by a surprisingly small increment: only $6. And that's $6 for the minimum order of 5 boards, not per board. Still, since I'm only using one of the additional two layers, it seems like I should be able to do it in four layers. As an experiment I merged ID board's interior signal layer with the power plane, and I get no DRC violations and no apparent orphaned islands. I've put off doing this until I finish all the routing, but I may be able to make the ID and ALU boards with four layers after all.