JLCPCB design rules for Eagle

A couple of days ago I "finished" routing the Instruction Decoder board. To be sure JLCPCB wouldn't have manufacturing problems, I used the same Eagle design rules file (DRU) I'd used to fabricate the Scratchpad Register board.

The Scratchpad board's DRU file started with the Eagle DRU file JLCPCB posted on GitHub for use with 2-layer boards which I modified for the 4-layer stack-up. Since JLCPCB's published capabilities allow tighter spacing on 4- and 6-layer boards I assumed this would be safe. The Scratchpad board works, but was this a good assumption?

The Scratchpad board is a 4-layer stack-up, with interior copper layers used as ground and power planes; all the signals routed on the top or bottom layers. The Instruction Decoder board turned out to be much harder to route so I upped the layer count from 4 to 6, with the inner-most two layers used to route signals I couldn't route on the outer two.

Interior layer tracks

When I finished routing the ID board I realized there weren't that many tracks routed on one of these interior layers and no tracks on the other. Rather than make a 6-layer board I'm probably going to merge the interior signal layer with the power plane layer and go back to a 4-layer stack-up. Using the minimum track-to-track spacing of 3.5 mil (0.09 mm) between signals and the power plane pour sounded sketchy, so I decided to take a closer look at the design rules.

As I compared the design rules in the DRU file I'd downloaded with the information published on JLCPCB's website, I found several discrepancies. The DRU file specified the wire-to-via clearance as 5 mil (0.127 mm) but the website gives this as 0.2 mm (7.87 mil), which is more than half again larger. Changing the wire-to-via clearance in the DRU resulted in about 45 DRC errors, which I addressed with minor changes in routing and via placements.

Then I noticed a discrepancy in the via annular ring size. The DRU file specified this as 3 mil (0.076 mm), while the website clearly documents this as 0.13 mm both graphically and in text. Changing this in the DRU file resulted in another dozen DRC errors requiring more layout changes, mostly to vias I'd already moved.

In a high speed digital design I'd be worried about clean signal return paths that don't cross an interrupted plane in the next layer down. However, my i4004 re-creation is not even close to "high speed". The fastest signal fall times are about 30 ns from 90% to 10%. Rise-times are even slower because of the use of resistive rather than active pull-ups. Thus I'm not really seeing the need for an uninterrupted power plane.

Maybe I'm just being obsessive, which is an occupational habit for a good software engineer where "close enough" is another way of saying "it's broken". I've changed all the feature-to-feature clearances to 8 mil (0.203 mm) and the board passes DRC. As a hobby project I get to make changes like this because it makes me happy.