The importance of return signal paths

In a comment on my post How high and how fast?, Klaus Scheffler pointed out that the "tiny wiggles" in my CLK1 signal could be significant if they exceeded the gate-source threshold voltage of a transistor acting as a transmission gate. He'd experienced issues with this in his implementation, which uses SST215 MOSFETs. Although the datasheet for the Calogic SST215 gives the typical Vgs threshold as 1.0V, the minimum is only 0.1V. My implementation uses the NXP BSS83 with the same specs, so this is a real worry.

[Note to self: the SST211 minimum Vgs[th] is 0.5V, which could provide the needed margin.]

Although I haven't experienced this sort of problem, I've only assembled two of the five boards that will make up my i4004 CPU. Could a problem be lurking in my future?

With another week to go before my next two boards arrive, I thought I should take a closer look at my clock lines. For these measurements both the Instruction Pointer and Scratchpad Register boards are plugged in, with the IP board on top. The yellow trace is CLK1, sampled at the gate of T0430 using a 1 GHz active probe. The blue trace is CLK2, sampled at the interboard connector on the right side of the board stack.

As CLK2 drives from ground to +5V, CLK1 first dips before briefly spiking to about +480mV. Then, as CLK2 drives back to ground, CLK1 first spikes to +200mV before dipping below ground level. Either one might be able to turn on a transistor when it should be off.

The only section of my boards where CLK1 and CLK2 run parallel for any distance is the  bottom edge of the Instruction Pointer board where they are parallel for about 4 inches. The tracks are 8 mils wide, spaced 25 mils apart, and are 15 mils above a solid power plane. That's not great, but I wouldn't think it would cause this much crosstalk.

To confirm, I removed the Instruction Pointer board from the stack and measured again on the Scratchpad Register board. I still saw evidence of crosstalk, though the effect was somewhat reduced. Maybe the primary source is somewhere else?

To allow testing of individual boards I'd built a test jig to interface with an FPGA reference board. This test jig includes 40 FDV301 transistors allow bidirectional data transfer while limiting the voltage driven into the FPGA's 3.3V I/O pins. This would not work, though for CLK1 and CLK2 lines, which need to be driven all the way to +5V. To do this the board also hosts a Microchip TC4427A MOSFET gate driver chip, which is the 8-pin DIP device at top-center of the board.

The TC4427A is capable of driving 1000pF to +18 in 20ns with matched rise and fall times. I'd originally acquired several of these as clock drivers for a project using an Intel 8080A CPU that never got built. It seemed like a good match for this project where CLK1 drives 28 gates (35, if you include the transit through T0047), and CLK2 drives 51 gates.

When I wired the TC4427A I anticipated it might generate some transients on the power supply. To buffer this I also wired a couple of 100nF ceramic capacitors and a larger tantalum capacitor across the power pins. While running this test I looked for noise on this IC's power pins but didn't see much.

While the top of the test jig board looks nice and tidy, the underside is a ratsnest. This picture was taken years ago, and has only gotten worse as I've added the connections needed by the Scratchpad Register board.

Of particular interest, though, are the CLK1 and CLK2 signals. These are carried on the orange and yellow wires visible in the upper left corner. They run next to each other, and while there appears to be a copper ground pour covering the surface of the board around the solder pads, that's a long way being an effective return plane for a couple of wires.

When I pinned out the connector carrying CLK1 and CLK2, I made the pins on the other side of the connector grounds. However, these pins were not connected to the ground on the test jig. This meant the return path current had to flow to the connected ground pins at the ends of this connector.

To see if this was related I ran a separate ground wire from these pins on the connector directly to the ground connection for the TC4427A driver. I routed this wire between the wires carrying CLK1 and CLK2, providing both separation and a close-ish return path. As shown here, this cut the peak induced in CLK1 during the rising edge of CLK2 by almost half, to about 210mV.

I'm hoping that once the hand-wired test jig goes away the crosstalk will decrease to a less troubling level. This won't happen until after I finish the I/O and Timing board, which is next in line.

One more thing... You know all the waffling I did regarding ground and power planes for the Instruction Decoder and Arithmetic Logic Unit boards? Forget it. I no longer feel the least guilt about making these six-layer boards.

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While researching the causes of crosstalk I came upon this video: What Every PCB Designer Should Know - Crosstalk Explained with Eric Bogatin. Eric Bogatin does an excellent job of explaining both capacitive and inductive crosstalk, with helpful graphics and no annoying math. I've found other videos recorded by Robert Feranec to also be worth watching, so it might be worth browsing his YouTube channel.