The importance of return signal paths

In a comment on my post How high and how fast?, Klaus Scheffler pointed out that the "tiny wiggles" in my CLK1 signal could be significant if they exceeded the gate-source threshold voltage of a transistor acting as a transmission gate. He'd experienced issues with this in his implementation, which uses SST215 MOSFETs. Although the datasheet for the Calogic SST215 gives the typical Vgs threshold as 1.0V, the minimum is only 0.1V. My implementation uses the NXP BSS83 with the same specs, so this is a real worry.

[Note to self: the SST211 minimum Vgs[th] is 0.5V, which could provide the needed margin.]

Although I haven't experienced this sort of problem, I've only assembled two of the five boards that will make up my i4004 CPU. Could a problem be lurking in my future?

Internal data bus pre-charging

I "discovered" an interesting feature in the i4004 internal data bus management this weekend. Maybe the rest of you already discovered this, but it's new to me.

With the Scrachpad Register board working with my test program, I decided to mate it with the Instruction Pointer board I built in 2012. One of my goals was to see if the CLK1 and CLK2 circuits would ring, or if the rise and fall times are slow enough to avoid problems. To my great relief, I see no significant undershoot or overshoot on these circuits, and no ringing at all. Whew!

However, my logic analyzer showed some suspicious timing on the internal data bus. At first it wasn't clear to me what was happening, so I probed around a bit with my oscilloscope. As I was making notes of my observations I realized what was happening, and this also explained a bit of circuitry in the original chip I didn't previously understand.

Actual CLK1/CLK2 rise & fall timing

 I finally had time to directly measure the rise and fall times of the CLK1 and CLK2 signals on my i4004 Instruction Pointer board. I'm hoping this will help me decide how to distribute these signals to the five boards of my i4004 CPU.

Treating CLK1/2 signals as global latch gate signals

If I were to change the Verilog i4004 emulation to treat the MCS-4 system CLK1 and CLK2 signals as latch gates and not as clock enables, it seemed it might make sense to treat them as I would global clock signals.

A clocking nightmare

Apparently I woo-hooed too quickly. I decided to run some simplistic simulations with LTspice to see what would happen with two boards connected to the output of a TC4427A. It wasn't good.

Alarming clocks

An email from a reader pointed out that the 50th anniversary of the Intel 4004's commercial release in only three years away (Nov 2021). I think it'd be a fun idea to have my discrete component implementation of the 4004 running by then, so I may have to kick my efforts up a bit.

As I've said many times before, I'm a software engineer by profession and have no formal training in electrical engineering. So it's not surprising when design decisions I made five or six years ago turn out to be questionable in light of recently acquired understanding. In this case, I'm talking about transmission line behavior.