When I last wrote in this blog last December I'd just completed Lesson 2 of FEDEVEL's "Advanced PCB Layout" course. By mid January I'd finished all the videos and then went back over several of the lessons I thought were most relevant. Robert Feranec is a good instructor with clear mastery of the topic.
As good as that class was, I still felt I needed a bit broader coverage. I've been doing digital design as a hobby for about 15 years, but I knew I was making some decisions based on guesses rather than good data. I decided to invest in FEDEVEL's "Advanced Digital Hardware Design" course, taught by Philip Salmony who also makes the "Phil's Lab" YouTube videos. The "Zett Brett" design he discusses in the video has many parallels with my latest project. I'd already completed much of my design by the time I started this course, but it gave me added confidence in many of my decisions.
Xilinx (now AMD) provides a spreadsheet for estimating the expected power requirements for each of the four power busses my design would require, but I didn't have much confidence in those numbers. In March I prototyped the entire power subsystem. I also used this to dip my toes into having my PCB designs assembled by the fabrication house rather than assembling it myself. Small steps rather than one huge leap.
By May I was facing my biggest, most critical challenge: the DDR3L DRAM layout.
The Zynq-7000 SoC has only 1 MiB of on-chip memory. My application is larger than this, so if the DRAM doesn't work any boards I made would be usable only for testing other interfaces. Some of my friends suggest I farm out this part of the design. Feeling particularly nervous one day I contacted a professional PCB design firm whose YouTube video on PCB signal integrity had impressed me. One of their senior engineers called me almost immediately and we discussed my requirements. For them, a single DDR3L DRAM interface running at "only" 533 MHz was a relatively easy job. The biggest sticking point was the tools.
Like many professional PCB design shops they use Altium, while I needed the design done with KiCad. Understandably, they didn't want to take on a job using tools they were not skilled at using. A PCB laid out using Altium would prevent me from doing my own updates in the future. This was the real deal killer. The other sticking point was money. They were willing to cut me a break on costs but, as he pointed out, their fee would be more than it would cost me to respin a failed design several times over.
These were not surprising issues to me, and I fully expected them to keep the conversation short. Instead the gentleman I was speaking with continued asking questions. He asked how much room I had on the board for the DRAM layout, because a common problem was trying to squeeze things too tightly; I replied that I had allocated a lot of room. We discussed the YouTube video that had led me to contact them. We discussed the capabilities of KiCad, and I was able to correct some of his outdated assumptions. He asked about my background and level of experience; I described a few examples of projects I had done as a hobbyist, and some of my professional work as an embedded software engineering consultant. Although I was enjoying the conversation, I kept thinking he must be having a really slow day to spend so much time on a job we both knew they weren't going to get.
About 40 minutes into the expected 5 minute conversation we wound down. He offered the opinion that I was heading in the right direction and would probably end up with a working DRAM interface. That felt good. Then, rather casually, he asked if I'd be interested in taking on some jobs with them. That took me totally off guard. Not as a PCB designer, I have to assume -- you could not pay me enough to do that job professionally. More for the skills I'd developed doing hardware design review from a software engineering perspective and doing board bring-ups. I replied that I was retired (or so I claim), and wouldn't even think about an offer like that until at least next year when this project was done. We said our goodbyes and ended the conversation pleasantly. I was left wondering how my design inquiry had turned into a job interview.
I spent all of June traveling. I normally work with a pair of 27" 2K monitors. A single 15 inch laptop screen is not conducive to complex PCB layout and I got almost nothing done. By mid July, though, I had what I felt would be an acceptable DRAM layout. Differential pairs are delay-matched within 1 picosecond. Each of the byte lanes and the address/control buses are internally delay-matched to within 2 ps. The main clock pair is deliberately routed to be slightly longer than any of the other signals by a few picoseconds. All basic requirements for a good DDR3L layout, according to the FEDEVEL classes I took.
The board also has Quad SPI Flash ROM and SD card interfaces. Having gotten used to using KiCad's delay matching capabilities I delay-matched these interfaces to with a couple of picoseconds. I resisted the urge to delay-match the 115200 bps serial port tracks.
In the middle of August I sent the board out for fabrication. It was a small run -- only 5 boards -- so the assembly set-up costs roughly equaled the cost of parts and PCB fabrication. Earlier in the design I'd felt I was being extravagant choosing an 8-layer stack-up, but the the final accounting puts that cost in perspective.
The boards arrived about a week ago. I'm still checking them out, but thus far everything is looking good. The JTAG works. The QSPI Flash works. The SD card works. The Zynq DRAM test application shows no errors, with an "eye" comparable to professionally-designed reference boards. The board boots from JTAG, QSPI Flash ROM, or an SD card, loads applications into DRAM and says "Hello World!".
Whew.
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