Showing posts with label FEDEVEL. Show all posts
Showing posts with label FEDEVEL. Show all posts

Wednesday, September 9, 2026

Skipping ahead 9 months...

When I last wrote in this blog last December I'd just completed Lesson 2 of FEDEVEL's "Advanced PCB Layout" course. By mid January I'd finished all the videos and then went back over several of the lessons I thought were most relevant. Robert Feranec is a good instructor with clear mastery of the topic.

As good as that class was, I still felt I needed a bit broader coverage. I've been doing digital design as a hobby for over 20 years, but I knew I was making some decisions based on guesses rather than good data. I decided to invest in FEDEVEL's "Advanced Digital Hardware Design" course, taught by Philip Salmony who also makes the "Phil's Lab" YouTube videos. The "Zett Brett" design he discusses in the video has many parallels with my latest project. I'd already completed almost all of my design by the time I started this course, but it gave me added confidence in many of my decisions.

Friday, December 5, 2025

FEDEVEL Advanced PCB Layout: Post Lesson 2 notes

I finished Lesson 2 of FEDEVEL Academy's Advanced PCB Layout course yesterday. As I expected, there ratio of review to new material (for me) is shifting toward the new stuff. There were a couple of confusing points, like the the instructor's strong recommendation to use a separate via for each power and ground connection on a BGA while watching him demonstrate routing two such adjacent balls to a shared via. Some of the recommendations  offered were things that I had read elsewhere, but it was nice to have it explained from another person's viewpoint.

And there were a couple of "Wait, what?" moments. 😯

Sunday, November 30, 2025

Taking FEDEVEL's Advanced PCB Layout Course

As part of a hobby project I'm designing a PCB that will include a Xilinx Zynq-7000 System-on-Chip and a DDR3L SDRAM. Both of these come in ball-grid array (BGA) packages with balls on a 0.8mm grid. This is my first attempt at a PCB using BGAs, but more critically, it's my first attempt with high-speed DRAMs.

I'm fairly confident, but at the same time I'm a little bit intimidated.