How high and how fast?

Most of the circuitry in the 4004 CPU and other MCS-4 family chips uses a MOSFET to actively pull a signal toward Vss, and a "load" to passively pull it back toward Vdd. In the real 4004 CPU, a "load" is a MOSFET with its gate connected to its drain, but designed so it works sort-of like a resistor. In my re-creation, a "load" is a real resistor.

When I did my initial breadboard tests of bits of circuitry, I used 10K ohm resistors for loads. I chose this value simply because I happened to have a bag of a hundred of 10K ohm axial resistors left over from another project. Given the low input capacitance of the two MOSFET types I am using (9.5 pF for the Fairchild FDV301N, and 1.5 pF for the NXP BSS83), it seemed a reasonable choice.

When I began assembling my boards, I worried that 10K loads wouldn't give good rise times. Back when TTL logic was standard it was common to use a 4.7K pull-up resistor on open collector outputs, so I used these instead. I also didn't understand how "bootstrap loads" worked, and thinking this was a rise time issue I used 2.2K resistors for these. This seemed to work pretty well on the Instruction Pointer board, but I had no engineering data to support these choices.

Eventually figured out the purpose of a bootstrap load. A normal load in the i4004 is unable pull all the way to Vdd, while a bootstrap load is able to pull a signal much closer to Vdd. I explain this in more detail in my post The Bootstrap Load mystery solved. Since a real resistor will pull very close to Vdd, I wondered if I could use 4.7K resistors in place of the bootstrap loads, but when I assembled the Scratchpad Register board I went with the same value resistors as with the Instruction Pointer board.

As I studied the Arithmetic Logic Unit board's schematic I noticed something strange. The ALU's carry prediction circuitry contains four nearly identical sets of logic, one for each of the data bits. The outputs of this circuitry (N0553, N0556 N0559, N0861) are push-pull drivers. Unsurprisingly, the loads pulling up the gates of the high-side drivers for bits 1 and 3 are bootstrap loads (B1871, B1873), as this allows the outputs (N0556, N0861) to pull higher. What struck me as strange is that the equivalent loads for bits 0 and 2 (R1870, R1872) aren't bootstrap loads.

I haven't figured out the reason for that yet, but I suspect it might be related to how bits 0 and 2 use inverted polarity from bits 1 and 3.

This got me wondering about my choices for load resistors. Were 4.7K and 2.2K good choices?  I now have two boards using these values and both seem to work pretty well. But I still didn't have any objective measurements to prove these choices as valid or not. It was time to get some real measurements.

Here's the bit of circuitry I looked at. This is part of the Instruction Pointer logic that controls precharging of the column sense lines. The input to T0430 on the right is driven by CLK1, which is a clean 5V square wave with fast rise and fall times. T0430 inverts this and drives only the gate of T0426.

On my boards both of these are FDV301N, which have a documented typical input capacitance of 9.5 pF, an output capacitance of 6 pF, and a Vgs threshold of 0.85V. The load, R1862, is a 4.7K ohm, 1% resistor. The track connecting these, N0522, is all of 18 mils (0.46 mm) in length so not a lot of capacitance there. I figured the total capacitance would be under 20 pF, giving a rise time to 3.16V (τ, or 63.2%, of my 5V Vdd) of about 95 ns.

I hooked my digital oscilloscope to the gate (red) and drain (blue) of T0430. My 500 MHz passive probes have an 9.5 pF input capacitance, so I expected to measure 140 ns. Instead, I was surprised to see 240ns. That works out to a capacitance of about 51 pF, which is a lot higher than I expected.

I tried the same measurement using one of my 1 GHz active probes on the drain, which add only 1.8 pF. This reduced the rise time somewhat, but it's still about twice the capacitance I estimated.

This is all probably related to some dynamic characteristic of MOSFETs I don't yet understand. This would not be the first time, and I'm sure it won't be the last.

 In this case neither the slow rise time nor the peak voltage is significant, as T0426 will be solidly on once its gate rises much above 1V, which takes less than 80 ns.

Of greater interest is what happens when T0412, T0422, and T0426 turn off. The load connected to their drains, B1859, then turns on the DRAM column sense precharge transistors in preparation for a DRAM row read. These 12 precharge transistors have their drains connected to Vdd and sources to the column sense lines, so as their sources rise their Vgs decreases and eventually they turn themselves off. In the real 4004, a bootstrap load is critical here because their gate voltages directly affect the sense line precharge voltages.

Here's what that looks like on my IP board, with the red trace connected to the the gate of T1313, the precharge transistor for bit 8 of the IP array. The yellow trace is connected to the bit 8 column sense line using an active probe.

When a DRAM cell is read, the column sense line becomes the inverse of the bit's value. In this instance the previously-read bit in this column was a 1, so the sense line was low before being precharged. When this bit is read it is also a 1, so the sense line is pulled low again.

In my implementation, B1859 is a 2.2K, 1% resistor. T1313 is a BSS83, with an input capacitance of only 1.5 pF. Adding 12 of these (18 pF) to the three FDV301N output capacitances (another 18 pF), I naively guessed this signal would have a total capacitance of under 40 pF. Subtracting the 'scope probe capacitance, it looks like the actual capacitance is closer to 80 pF. Oops.

Note here that the gate voltage never reaches Vdd of 5V, barely topping 4.4V even at the end of the 440ns CLK1 pulse. The 4004 datasheet allows the clock pulses to be between 380 and 480 ns, so a shorter clock pulse would lower the peak voltage by maybe 0.1V. 

The BSS83 datasheet unhelpfully gives the Vgs threshold voltage as a minimum of 0.1V and a maximum of 2.0 volts. (The datasheet for the CaLogic SST215 Klaus is using states the typical is 1.0V, but retains the same wide min/max range.) In this configuration, with the substrate at 0V and the source rising to 2.5V, T1313 appears to turn off with a Vgs of 1.9V. Fortunately for me the sense amplifiers (T1145 for this column) are FDV301N with a threshold voltage far below 2.5V; even a BSS83 would work.

What would have happened if I'd used a 4.7K resistor instead of 2.2K to replace the B1859 bootstrap load? Assuming a circuit capacitance of 80 pF, the math says the peak gate voltage after 440 ns would decrease from 4.6V to 3.4V, a loss of 1.2V. This would reduce the sense line precharge voltage to about 1.5V, which is getting close to the threshold voltage of an FDV301N as the sense amplifier. With a BSS83 as the sense amplifier you'd be below the maximum threshold of 2.0V, though still above the typical 1.0V.

How about a 10K resistor? The peak gate voltage after 440 ns would be just 2.1V. Allowing for even a 1V Vgs threshold* in the precharge transistors doesn't leave a safe margin for the sense amplifiers to respond. So while 10K probably would have worked as R1862, it would not have worked reliably if at all for B1859.

Maybe I guessed good resistor values after all?

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*Why am I decreasing the threshold voltage here? In a BSS83 (and SST215), the source is not internally connected to its substrate (also called its "body"). This is essential for using a MOSFET as a transmission gate. However, Federico Faggin explains that the "body effect" causes a MOSFET's threshold voltage to increase proportionally with the square root of the voltage difference between the source and substrate (Vsb). The 2.5V source-substrate difference likely accounts for much of the 1.9V gate-source difference I observed on T1313. With a lower Vgs the source wouldn't rise as high, and the smaller Vsb would also reduce the body effect increase in the threshold voltage.