The Fit-Test board has paid for itself

The fit-test board I had fabricated has paid for itself!

This is the footprint for a TI TPD4F003 four-channel EMI filter with ESD protection. There are two on this board. This one protects the JTAG interface and the other protects the External I/O interface. It's a tiny little device, measuring only 1.80mm x 1.45mm, with pads on 0.40mm centers. For comparison, the pads on the JTAG connector visible in the lower right corner are on 2.00mm centers.

It's a little hard to tell because of the glare in this photo, but while the large rectangular ground pad in the middle is exposed, the four signal pads on each side are covered with solder mask. This would cause me serious trouble, as I'd have to try to scrape the solder mask off the copper pads before soldering the part in place without causing too much damage to the pads that are only 0.25mm wide. Even then I'd be soldering to bare copper rather than prepped with ENIG.


I took a look at this footprint in KiCad, and there are indeed solder mask apertures defined. Here is a screen capture of the Gerbers I sent to JLCPCB, as viewed using GerbView. The green areas are the solder mask apertures.

What went wrong? My best guess at this point is that the apertures are too small for JLCPCB's process to handle, so they got dropped. I looked for a specification for their minimum solder mask aperture and couldn't find one. Since I left out the inner two layers of this four-layer board I specified that I didn't want it electrically tested. Maybe they would have caught this if I had.

My plan is to edit the footprint and enlarge the solder mask apertures for the signal pads enough so they overlap, as they do on the FPGA which has pads on 0.5mm centers. I'll probably also note this problem in the "Remarks" section of the fabrication order and reference the previous job number. Four-layer boards are always electrically tested (and I'd ask for it if it wasn't) so that may help avoid this when I have the real board fabricated next week.