Data bus charge redistribution

In my previous post I mentioned an anomaly I'd noticed in the data bus state during a period I believed it should be floating but stable.

Klaus Scheffler mentioned in his comments that he'd seen the same thing on his board. This got me wondering if I could use the simulator to help me understand this behavior. Sure enough, the sim also shows an indeterminate state on the data bus under similar conditions.

This snapshot of the simulator shows the X12/X22/X32 subcycles of the SUB instruction at address 069, and the A12 subcycle of the instruction at address 06A, in the default test program. Above the data bus we see the subcycle timing signals, while signals below the data bus control access to the data bus in some way. Note that while a "high" state on most of these control signals connect a subcircuit to the data bus through transmission gates, N0676 works the other way: a 0 enables tristate drivers in the I/O buffers to drive the data bus.

In each of these subcycles, when CLK2 is high N0659 also goes high. N0659 is the signal that pre-charges the data bus to all ones. Between CLK2 going low in X22 and it going high again in X32, the data bus is floating, as indicated by the dotted trace line. However, when CLK1 goes active during X32, D2 and D0 change from a floating high state to an "in-between" or undefined state.

The only control signal that has gone active during this period is descriptively-named "M12+M22+CLK1~(M11+M12)". This signal gates the data bus to the inputs of both the instruction pointer and scratchpad register subsystems. At first I dismissed this as a cause of the anomaly, this doesn't connect any sort of output driver. They're inputs, right?

Scratchpad board only

Remember, though, that the data bus is floating. This means the only thing keeping it at a stable state are the charges stored on the capacitance of the wires and devices wired to them. Connecting one FET gate to the data bus doesn't cause much change in the bus voltage, as there is only a small capacitance to charge from the bus. This image shows what happens when only my Scratchpad Register board is connected. Note the small but perceptible drop in bus voltage during X32/CLK1 as the gate of one FET is added to the load on D0.

SP and IP boards

I expected the Instruction Pointer circuit to be similar. And it would be, if not for the IP incrementer. The incrementer is the circuit that increments the instruction pointer as the instruction address is output during subcycles A1/A2/A3. This circuit adds more loads to the data bus lines. In the case of D3, "M12+M22+CLK1~(M11+M12)" going high adds one FET gate for the Scratchpad and three for the Instruction Pointer, for a total of four. However, In the case of D0, this adds seven FET gates: one for the Scratchpad and six for the Instruction Pointer.

Now the explanation becomes clear. When the inputs to the Instruction Pointer and Scratchpad boards are enabled, the charges must equalize. If the two sides of the transmission gate are at the same level, nothing much  happens. But if they're different the charge on the bus flows through the transmission gate until they equalize. In this case, they equalized at just under 2V.

So is this a problem? No. This is an acceptable behavior because nothing cares what the state of the data bus is during this period.

I have to say I'm impressed that the simulator even recognizes and correctly displays this situation. Kudos again to Lajos Kintli!