DRAM testing methodologies

Since I decided to do proper testing of my Scratchpad Register board, I thought I ought to invest some time in understanding the type of faults a DRAM array might have, and how to test for them. Given that the array on this board is only 8 rows of 8 bits I'm not really concerned with run-time, but I do want the tests to be thorough.

In my search for useful algorithms I came across this series of videos by Professor James CM Li of the National Taiwan University:

• 16 1 MemTest Intro (32:25)
• 16 2 Memory Test - Classical algorithms (23:41)
• 16 3 MemTest March (25:18)

These are part of a much longer online course (94 videos) on VLSI Testing, but these three address testing RAM. The total run time for all three is only 1 hour 21 minutes. Professor Li speaks English with a pronounced accent, but his pace and careful enunciation make him easy to understand (unlike several videos by others I tried to watch).

I think I caught one small error in his explanation of the answer to one of his "quizes", but otherwise the content seems solid and is explained well.

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DRAM tests look for three classes of faults:

• Address Decoder faults
• Memory Cell faults
• Dynamic faults

A good test algorithm will detect all of the first two classes, and may detect some of the third.

The most common DRAM testing algorithms march through the array, testing each bit to make sure it can be set to zero and one, reads back with the proper value, and isn't affected by operations on other bits in the array. These algorithms are referred to as March algorithms.

Initially, I'm planning to implement the "March C-" algorithm:

1. Write zeros to all bits in the array.
2. For each bit in ascending address order: read the bit and verify it's a zero; write the bit as a one.
3. For each bit in ascending address order: read the bit and verify it's a one; write the bit as a zero.
4. For each bit in descending address order: read the bit and verify it's a zero; write the bit as a one.
5. For each bit in descending address order: read the bit and verify it's a one; write the bit as a zero.
6. Read every bit (order irrelevant) and verify it's a zero.

The initial zeroing of the array will (should?) be accomplished by the eight instruction cycles executed with POC (power-on clear) asserted. The read/write sequence can be executed through the signalling generated by the i4004's XCH instruction. This instruction causes the selected scratchpad register to be read during subcycle X22, and written during subcycle X32. The final read can be done using the LD instruction, which is basically the same as the XCH instruction without the write during subcycle X32.

Later I'll add tests that read and write register pairs by emulating the SRC (or JIN) instructions to read register pairs, and FIM instructions for to write register pairs.

Dynamic faults are sensitivities to timing or repetitions. For example, there is normally a refresh cycle during the A22/A32/M12 subcycles for each instruction. Thus, a Scratchpad register is normally refreshed every 8 instructions. However, refresh cycles are suppressed during the second instruction cycle of a double-cycle instruction. If a series of double-cycle instructions are executed, the normal refresh frequency could be cut in half.