A sixth board?

When I started this project I was very worried about how I'd test this thing. I didn't want to build all five boards, only to discover I'd made some major mistake that would require scrapping them and starting over. Doing so would not only take a lot of time, but between the cost of the board and the components on it, each assembled board costs around $250. Redoing one would be frustrating and annoying, but if I had to redo all five I might well drop the project.

Starting the I/O and Timing board

I figured the best way to be sure all the right components got on the I/O and Timing board was to create an Eagle project for it. So I did. And promptly realized that a lot of the Eagle configuration I'd gotten used to has to be done on a per-board basis, like trace width and via drill diameters. This is the first i4004 board I've started since late 2012, and you can forget a lot in three years.

There are three major functional groups on this board:

1. A self-initializing 8-bit shift register that produces the one-hot CPU phase of execution signals (A12, A22, A32, M12, M22, X12, X22, X32) and the SYNC signal.
2. The 5-bit Chip Select decoder and external output drivers (CMROM, CMRAM0 to CMRAM3). This is the chunk of logic that I moved off the ALU board.
3. The 4-bit, tri-state, bi-directional data bus external pin I/O drivers.

I haven't made a screen shot of the layout yet. I'm at about the half-way point, with the first two groups placed and partially routed. The layout is moving so rapidly because there is a lot of repetition within each group. The shift register is essentially 8 copies of the same 1-bit pattern, with a minor variation on the first (A12) and last (X32) bits, plus some logic to generate the SYNC signal. Once I found a layout that worked well for two adjacent bits the rest follow the pattern. The five Chip Select output drivers are all the same and the decode logic has common elements. I haven't started laying out the data bus I/O drivers yet, but it will be four instances of the same layout pattern -- one for each bit -- plus a little decode logic.

I expect the parts I've already placed will shift position (and possibly rotate in the case of the Chip Select logic) to accommodate the data I/O drivers but I don't expect any problems making it all fit. This board has the fewest components of any board in the set and there's quite a bit of free space left.

A reminder to myself

I got to thinking about the I/O and Timing board last night, and discovered I hadn't started an Eagle project for it. This is a worry, because in September 2012 I did A little re-partitioning which involved moving the ROM/RAM chip select logic and drivers off the ALU board and onto the I/O and Timing board; a board for which a project does not exist. I don't want to lose this change.

With any luck this change was just moving an entire schematic sheet from one board project to another, but I have suspicions that it involved splitting Sheet 13 of the partitioned master into two separate sheets. Since I no longer remember what did and didn't stay in the ALU project I need to go back to the partitioned master and compare that with the ALU schematics so that chunk of logic doesn't get lost when I create the IOT board project.

Preliminary Scratchpad placement complete

I was having trouble getting to sleep last night, so I finished placing the remaining components on the Scratchpad board. Here's a screenshot:

With plenty of free space on the board I kept the components making up the various functions grouped and separated. The DRAM array is pretty obvious. The row drivers are to its immediate right, column pre-charge above and column sense and mux below. The control and data busses are below that (on the bottom of the board, shown in blue), and the write data latches below those.

Outlined on the right edge of the array are the row read and write enable drivers, and to their right is the 3-to-8 row address decoder. Continuing to the right is the 3-bit refresh counter, with each bit outlined. Bit 0 is on the bottom and bit 2 is on the top.

The other groupings are logic functions to generate various signals such as read and write enables for the odd and even nibbles, row read and write strobes, etc. When placing these groups I worked from the output drivers back toward the input signals. I started laying them out left-to-right, but after finishing them I decided they'd work better with each group rotated 90 degrees clockwise. Originally the order of the groups was the same as in the schematic, but I've since rearranged them into what seems better from a signal routing perspective.

Speaking of routing, I also routed the refresh counters and the row decoder logic. This seemed to be the easiest way to be sure the layout was workable. There's still a lot of routing to be done: there are 639 signal airwires, plus 424 ground and 84 VDD airwires. I also need to add power decoupling capacitors, and decide whether to add provisions for charge storage capacitors in the DRAM array as I did with the IP board.

Scratchpad refresh counter placement

Thinking how to best pin out the rest of the inter-board connections, last night I decided I should also look at the Scratchpad board. To my surprise I discovered I really hadn't gotten much done on this when I shelved this project back in 2013. Looking back at the blog entry I wrote about Scratchpad Array Placement in August 2012 I see I'd done the placement of the rectangular DRAM array components but not much more. Almost none of the signals are routed.

Progress on the ID board

I took a look at the Instruction Decoder board this evening and discovered there were a handful of parts that not only hadn't been routed at all yet, they weren't even in a near-final placement. I really thought I'd gotten farther on this than I had.

It wouldn't show up on a screen shot so I'm not going to bother, but I juggled most of them into a reasonable layout and routed within the groups. I also took a look at what's left unconnected and, like the ALU board, switched from a 4-layer to a 6-layer stackup using the same layer assignments as the ALU.

Ratsnest now reports 16 VDD, 32 GND, and 85 other airwires. That's after I'd already routed a bunch of unconnected GND pads. Again, I'm a bit surprised these numbers, especially the number of GND airwires.

There's still some possibility that as I get close to the final routing I'll decide to go back to a 4-layer board. Since all the components except the connectors are surface-mount, I've routed as much as practical on the top layer to minimize the number of vias (and thus minimize the board area they occupy). Looking at only the bottom and inner layer there really isn't that much there. If it's practical to route the remainder using only these two, and if the power distribution will also fit, I might dispense with the extra two layers. Or maybe not.

Progress on the ALU board

With six copper layers to play with, routing the ALU board has gone from challenging (if not nightmarish) to relatively easy. When routing vertical traces I no longer have to consider how I'm going to get VDD to the various pads, and routing nets to the connectors is mostly a matter of keeping routing lanes free of vias to avoid having to weave around them.