Saturday, September 15, 2012

A little re-partitioning

While coding the Verilog version of the i4004, I came to realize there's a group of circuits I originally assigned to the Instruction Decoder board that is really part of the ALU.

At the same time, there's a group of I/O circuits on the ALU (the ROM/RAM chip selects) that I'd really rather have on the Timing and I/O board, just to keep all the I/O drivers together.

I think the number of components to be moved off the ALU just about matches the number of components to be moved onto it, which will help keep the density manageable. It's actually a net reduction in inter-board connections, though there still are plenty of uncommitted pins on the connectors.

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