Monday, June 26, 2017

Another observation on test equipment

Years ago I bought myself a 4-channel 1 GHz digital oscilloscope. The four probes I got with it are the typical x10 passive type rated to 500 MHz. For my purposes this has always been good enough.

At work last week we needed to look at an async serial line at a weird bit rate of almost (but not quite) 10 Mbps. My co-workers found two very fancy digital oscilloscopes but couldn't find any probes to go with either scope. Noting that the simpler of these scopes was rated for 3.5 GHz I realized we wouldn't be looking for the normal cheap passive probes, and found a set of active single-ended probes rated for 3.5 GHz and another set of differential probes rated for 1 GHz, each carefully stored in custom carry cases. Selecting the appropriate probes for the job I cautioned my programmer co-workers to be careful with these probes, as they were probably worth $5,000 each.

Apparently that sounded like hyperbole to the youngest of my co-workers, but rather than disregard my caution he took the time to look for the going price for them. A couple of days later he told me that my $5K guess wasn't quite right: they're only worth $4,500 each. He said it in a matter-of-fact tone, but it was pretty clear that he was surprised that I really wasn't exaggerating as he'd thought.

This got me wondering what a 1 GHz active probe would cost for my scope. I found several such probes in used but calibrated condition for under $100 each. I've never really needed one, but now I'm wondering if I shouldn't buy one while they're available.

Monday, May 22, 2017

Other insane hobbyists

Recently I've been shown that I'm not the only hobbyist with a touch of insanity.

I've already mentioned the folk behind who have resurrected the 45-year-old Intel design for our education.

There's Robert C. Baruch, the self-named Half-Baked Maker, who is entertaining himself by reverse-engineering some old integrated circuits by stripping them layer by layer to develop a schematic diagram of their workings. This requires the use of nasty chemicals like hydrofluoric acid -- and people think I'm nuts for using tin/lead solder!

Personally, I think the person who most deserves the crazy inventor award is Sam Zeloof. He's creating working MOSFET transistors in his home laboratory. He recently acquired his own scanning electron microscope; can an unlicensed nuclear accelerator be far off?

My hat's off to you folk. You make me feel totally sane.

Monday, May 15, 2017

Packing worms into a can

Back a few years I threw the Verilog source code for the 4004 CPU at the Lattice toolchain and observed that it occupied "40% of the logic cells and one of the 16 block RAMs" of an iCE40-HX1K FPGA. From this I felt that using an iCE40-HX4K part, which is 2.75 times the size, would be plenty to implement the entire Busicom 141-PF calculator system. Of course it'd be even nicer if I could use the HX8K part, 6 times the size of the HX1K, but it's only available in a BGA.

While trying to get the comma positioning working in the VFD driver code I took a look at the resource utilizations for two potential implementations. What shocked me was not the difference, but the total size: 492 of the 1280 lookup tables (LUTs). That's 38%!

Once I caught my breath I asked myself how this compared with the Xilinx parts I've worked with. So I built the same Verilog code using Xilinx ISE 14.7, specifying a Spartan 6 chip; it used 331 LUTs. However, the Spartan 6 has 6-input LUTs, versus the 4-input LUTs of the iCE40. Trying to find a more apples-to-apples comparison I built it yet again, this time specifying the Spartan 3E chip which also has 4-input LUTs. The Spartan 3E used 320 LUTs. Advantage Xilinx, whether by better architecture, better synthesis, or both.

But what was using all these LUTs? I thought over my code and really couldn't see any real hogs. Most of the selectors in the case statements are 4-bit quantities, which should require only one LUT per output bit to implement. Looking at the Xilinx ISE Map report I noticed a section for "Utilization by Hierarchy." Excellent! I enabled the detailed Map report and reran the mapper. To my great surprise it is the Digilent Adept I/O Expansion interface that is taking up the majority of the LUTs: 205 of 331 in the LX9, and 157 of 320 in the S3E. (I don't know how to get the same statistics out of the Lattice version of Synplify Pro).

While it's certainly a relief to find my VFD driver isn't the hog I thought it was, it does point out the risk of underestimating resource utilization. The Adept interface doesn't look very complicated -- it's only about 100 lines of Verilog -- but it takes a lot of resources. For comparison, the entire 4004 CPU and one 4001 ROM, which I think of as complex, requires only 400 S3E LUTs.

So back to the choice of chips for the calculator. I found I was able to do more with ISE in a shorter time, though whether that's better integration or just greater familiarity I'm not sure. The Xilinx tools and chips seem be more efficient in their use of resources than the Lattice. Finally, I can get the Spartan 6 LX9 in a TQFP-144 package, while the iCE40-HX8K is only available in a 0.8mm-pitch BGA. Yes, mounting a BGA scares me, but more importantly it would be infeasible with this design unless I made the board with blind vias and that would really jack up the cost.

I think that settles the matter. The Lattice iCE40 series is quite reasonable to work with, if you're looking for something small, power efficient, or are willing to stick with commercial boards. The toolchain is quite acceptable, even if you do have to obtain a new (free) license every year. But for my specific needs, I think the Spartan 6 LX9 is the best fit.

Why not Altera? They make fine chips. The answer, simply put, is that I don't know Altera, I don't have any equipment to program them, and I just don't have time or interest in adding yet another variable. They do see to have quite a selection of chips in hobbyist-friendly (i.e. non-BGA) packages, though. Some other project, perhaps.

Saturday, May 13, 2017

Not too shabby

Here's the Vacuum Fluorescent Display salvaged from the Canon P170-DH calculator driven by a Lattice iCE40-HX1K FPGA through my driver test board.

Tuesday, May 9, 2017

More data, but not more understanding

I continued poking around my VFD driver test board, looking for an explanation for why I need such strong pull-down resistors on the VFD grids. I know more than I did, but I still don't understand why.

Saturday, May 6, 2017

Who ya gonna call?

Grid Driver Configuration
I decided to dig deeper into the ghost segments appearing on the VFD.

The Toshiba RN4604 I used in the anode and grid drivers contain two pre-biased bipolar transistors, one PNP and one NPN; the bias resistors are all nominally 47K ohms. Driving the CTRL input to +3.3V turns on Q1B, which drives Q1A into saturation and pulls the grid to +30V. With the CTRL input at ground Q1B and Q1A are off, and R2 pulls the VFD grid to ground. The ends of the filament swing ±2V around a point +6.8V above ground, so an inactive grid should be at least -4.8V with respect to the nearest filament segment.

I connected my oscilloscope to the VFD grid leads for the active and ghosting digits. When the active digit's grid went to +30V with respect to ground I saw the ghosting digit's grid rise to about +10V. That's about +3V wrt to the average cathode voltage, which attracts enough electrons to cause the active anode in that digit to fluoresce too. Although this is not a truly stable state and tended to dissipate over time, it appeared the pull-down resistor R2 wasn't doing its job.

Just to be sure I looked for any indication that the ghosting digit's grid driver was turning on spuriously, but I couldn't find any. The circuit is sensitive enough to turn on momentarily if you touch an undriven CTRL input, but wiring CTRL to ground didn't change the behavior. Scoping the input to the PNP transistor showed nary a wiggle even as the grid lead voltage rose.

I expected some leakage current on an inactive grid, but the datasheets I saw for ICs that had built-in pull-downs used 125K ohm resistors so I wasn't expecting much current on an inactive grid. I tried placing a second 100K ohm resistor atop the existing 100K pull-down resistor, giving an effective 50K ohm pull-down, and although that reduced the brightness of the ghost segment it didn't eliminate it. Given 10V across 100K ohms, the leakage current on the ghosting digit's grid must be about 100 uA. Hanging a through-hole 10K resistor to ground on the lead killed the ghost. That's probably excessively low, but I haven't been able to find any information on this VFD that would give an expected inactive grid current.

My best guess at this point is that there is some capacitive coupling between the grids within the tube, and it causes the adjacent grid to rise. The condition isn't stable because the charge eventually bleeds off through the pull-down resistor. But I don't really understand the mechanism at work here.

I don't have a lot of 0603 SMD resistors laying around so I decided to replace the 100K pull-downs on the grids with 10K resistors. This will cost me an extra 3mA on the active grid, but there's only one grid active at any time. Active anodes draw less than 600uA each, while there are always 2 to 9 anodes lit per active digit, so I decided to leave their pull-downs as 100K resistors.

Next I'll work on getting the FPGA to drive this thing.

Friday, May 5, 2017

Some Assembly Required

After spending an exhausting day listening to multiple presenters talking non-stop about the project at work, I was ready to do something completely different: assemble my VFD driver test board!

Here's a bare board sitting on the connectors to the Lattice iCEblink40-HX1K demo board I'm using as a driver test driver.