Tuesday, July 10, 2018

Demonstrating the SAP-1 Program Counter bug

Simulation is all fine and well, but the proof is comparing the results of the simulation with the real circuit. So I did just that.

Thursday, June 28, 2018

A structural version of the 74LS107A

Since I'd tested a structural simulation of the 74107 master/slave J/K flip-flop, I thought it appropriate to also test a structural simulation of the 74LS107A edge-triggered J/K flip-flop. The datasheet for the SN74LS107A from Texas Instruments provides a schematic for their chip, so I started there:

Monday, June 25, 2018

Last attempt with the M/S J-K Flip-Flop

With nominal gate delays added to all the TTL parts in my SAP-1 Verilog simulation, I decided to give the Master/Slave version of the 74107 J-K flip-flop one more try. And it flopped.

Sunday, June 24, 2018

A minor bug in the SAP-1 design

I put delays into the components used in the SAP-1 computer to better simulate the real chips. These delays are tiny compared to the 1 millisecond clock cycle of the SAP-1 -- generally on the order of 10 to 50 nanoseconds -- but they broke the simulated system: the RAM wasn't getting loaded with the correct values. I tracked this to the 9 ns propagation delay of the RAM address passing through the 74LS157 2:1 mux. A minor change in the timing generated in the testbench during these operations restored proper behavior.

BUT... while investigating this I discovered a bug in the SAP-1 design, and this one is not my fault.

Miswired adder... and the SAP-1 works

I found the "last" bug in my Verilog implementation of the SAP-1 computer. It looks like I did a cut-and-paste of the instantiation of the 74LS83 adder for the high-order 4 bits (C16) to create the instantiation of the adder for the low-order 4 bits (C17). I then connected the carry-in and carry-out signals correctly for both parts, but I forgot to change the bit numbers for C17. Thus the low-order bits weren't being driven.

Fixing this allows the SAP-1 to execute all 6 instructions of its program and produce the correct output on the emulated LEDs.

As satisfying as this is, it is not the purpose of recreating the SAP-1. The purpose is to help me understand more clearly how a computer fetches, decodes, and executes instructions.

Saturday, June 23, 2018

A bug in the SAP-1 Program Counter?

This morning I figured out what I did wrong with the SAP-1 Program Counter. But I think I also found a potential bug in the original design.

Friday, June 22, 2018

A good starter book

While browsing the web I came across some interesting references to a
textbook called "Digital Computer Electronics" by Malvino and Brown. Originally published in 1977, and updated in 1983 and 1993, this book is out of print but still available on the used book market. One of the features is the step-by-step design of a simple computer the authors call the Simple As Possible computer, or SAP.

I've been tinkering with digital electronics since the Intel 8080 was new. I built a Science Fair project from TTL gates and circuits when I was in 9th grade (1976-ish). Thus the basics of digital electronics in general, and TTL circuitry in specific, are quite familiar to me. However, the opportunity to look at the instruction decoding and state transitions of a computer was quite appealing, and I hunted down a copy.

As is to be expected of a book last updated 25 years ago, the material is somewhat dated. The low-power Schottky TTL gates that were cutting edge then have been all but replaced by faster, more efficient CMOS technologies that this book notes in passing as low-power but very slow. That said, the design techniques are still valid. A NAND gate is still a NAND gate, even if the technology used to implement it is different.