Monday, December 31, 2012

An interesting coincidence

It's New Year's Eve for most of us  who use the Gregorian calendar, and New Year's Day for those more than 10 hours east of me. Best wishes to everyone!

I was browsing around the other day, and I noticed the following announcement in the Intel 4004 35th Anniversary site:
Coming soon: Synthesizable Verilog source and testbench for the 4001 ROM, 4002 RAM, and 4004 microprocessor.
They're doing one too! Or... are they planning to link to or repost mine, once I get the rest of the Verilog posted? I'd like to think so, but I would have thought I'd have gotten a "that's a cool project!" email by now. Not that they're obligated -- most of the code is under the Creative Commons license. Maybe they're just shy? :-D

Regardless, there will be updates. It's just that they're moving at the speed of boredom: the more bored I am the faster they move. Recently work has been very not-boring, which has slowed the pace of my hobby projects.

ALU board progress

I've been working on the Arithmetic Logic Unit board layout. I have roughly placed all four bits of the data path (bit 0 at the top, bit 3 at the bottom) and the Keyboard Process logic. This accounts for 67% of the transistors with plenty of area left over.

I've done very little routing yet. With the Instruction Pointer board I was able to route everything using just the top and bottom layers, reserving the inner layers for unbroken ground and power planes. That isn't going to work on this board. I briefly considered a 6-layer board, but that seems like gross overkill. I spent some idle time perusing my copy of High-Speed Digital Design, A Handbook of Black Magic, and have come to the conclusion that while keeping an unbroken ground plane will be advantageous, there's little point in fighting hard for a power plane.

My rationale is that most of the FETs are wired in a grounded-source configuration, which makes them respond to gate inputs with reference to ground. The FDV301N is designed to work in low voltage circuits, and is only specified to remain off with an input at or below 0.5V; its Vgs(th) is as low as 0.70V. Thus a negative ground bounce of less than a volt could easily cause one to turn on when it should be off. In contrast, a droop of even several volts in the Vdd supply really won't affect them.

The only place where the Vdd supply voltage is critical is the drive to the BSS83N pass-gate FETs; except for these, I could run the entire CPU on 3.3V. Of secondary concern are push-pull drivers, due to the Vgs drop across the pull-up transistors. I expect  reasonable bypassing will take care of both these problem areas.

This frees up one of the inner layers for routing. My stack-up plan now looks like this:

Layer # Use
Top 1 Local connections
Inner 2 Ground Plane
Inner 3 Vertical connections
Bottom 16 Horizontal connections

In my last posting I said I might rotate the bit paths 90 degrees. I did give that a try. However, I hadn't placed the last of the components in the paths, and it got a bit tight. Further, it became more difficult to mentally translate from the schematic to the board. In the end I switched it back around.

Tuesday, December 4, 2012

Starting the ALU board

The instruction decoder and the arithmetic/logic unit are so tightly coupled that they really should be on one board. Of the 70-some inter-board connections, better than one out of three connect only these two boards. Thus it makes sense that the layout of these two boards, and the pin-out of the remaining connector pins, be accomplished in parallel.

Here's the start of the ALU board layout:

As with the other boards, I've used "wires" drawn on one of the documentation layers to sketch out the various pieces. The four horizontal areas containing components represent the four-bit data path through the ALU. The right-most group forms the input value "register" (really a transmission gate to capture the data bus, two inverters to generate true and inverted versions of the data bit, and a pair of push-pull drivers). Moving right to left, the remaining groups are the carry predictor, the carry output driver, the adder, and the true/complement selector. The group on the far left is a combination of the bidirectional shifter and the accumulator register. Since the accumulator's value may need to remain stable for long periods of time, it includes a built-in refresh circuit to keep the charges from leaking away.

The odd collection of rectangular areas in the lower left represent the so-called "Keyboard Process" logic, a translation table of sorts that converts a one-of-four accumulator value (0/1/2/4/8/*) into a 4-bit binary output value (0/1/2/3/4/15). I was surprised to find such a function implemented in hardware, but apparently they felt it was a reasonable speed vs silicon area trade-off.

There's still a good bit of circuitry to be placed on the board outside of the sketched areas. The original layout of the data path occupied the entire width of the sketched area, but clearly that can be narrowed significantly. So much so, that I may rotate the whole area 90 degrees. We'll see once I get some routing done.

Clearly I'm not going to have boards ready to be fabbed in time to get them back by Christmas. But maybe I'll be able to spend some of my holiday break on the project.