I've done very little routing yet. With the Instruction Pointer board I was able to route everything using just the top and bottom layers, reserving the inner layers for unbroken ground and power planes. That isn't going to work on this board. I briefly considered a 6-layer board, but that seems like gross overkill. I spent some idle time perusing my copy of High-Speed Digital Design, A Handbook of Black Magic, and have come to the conclusion that while keeping an unbroken ground plane will be advantageous, there's little point in fighting hard for a power plane.
My rationale is that most of the FETs are wired in a grounded-source configuration, which makes them respond to gate inputs with reference to ground. The FDV301N is designed to work in low voltage circuits, and is only specified to remain off with an input at or below 0.5V; its Vgs(th) is as low as 0.70V. Thus a negative ground bounce of less than a volt could easily cause one to turn on when it should be off. In contrast, a droop of even several volts in the Vdd supply really won't affect them.
The only place where the Vdd supply voltage is critical is the drive to the BSS83N pass-gate FETs; except for these, I could run the entire CPU on 3.3V. Of secondary concern are push-pull drivers, due to the Vgs drop across the pull-up transistors. I expect reasonable bypassing will take care of both these problem areas.
This frees up one of the inner layers for routing. My stack-up plan now looks like this:
In my last posting I said I might rotate the bit paths 90 degrees. I did give that a try. However, I hadn't placed the last of the components in the paths, and it got a bit tight. Further, it became more difficult to mentally translate from the schematic to the board. In the end I switched it back around.