Monday, December 31, 2012

An interesting coincidence

It's New Year's Eve for most of us  who use the Gregorian calendar, and New Year's Day for those more than 10 hours east of me. Best wishes to everyone!

I was browsing around the other day, and I noticed the following announcement in the Intel 4004 35th Anniversary site:
Coming soon: Synthesizable Verilog source and testbench for the 4001 ROM, 4002 RAM, and 4004 microprocessor.
They're doing one too! Or... are they planning to link to or repost mine, once I get the rest of the Verilog posted? I'd like to think so, but I would have thought I'd have gotten a "that's a cool project!" email by now. Not that they're obligated -- most of the code is under the Creative Commons license. Maybe they're just shy? :-D

Regardless, there will be updates. It's just that they're moving at the speed of boredom: the more bored I am the faster they move. Recently work has been very not-boring, which has slowed the pace of my hobby projects.


  1. Hi Reece,

    Tim from the 35th anniversary project here. Yes, of course you deserve a "that's a cool project." And indeed it was a coincidence. We've long-since written and verified the Verilog promised on our web site. It's what's been running on the FPGAs inside the museum exhibit we installed in 2006. The publishing/posting delay is because we haven't had time to clean up and package the Verilog code and to include a test-bench so folks can play with it right away. We actually have two versions: a synthesizable one that's written at the register-transfer-level (RTL) and one that was derived automatically from the netlist. The latter we used for verifying our schematics.


    1. Hi Tim!

      I assumed you had some models of the 4004, but I didn't know you had a synthesizable one. What techniques did you use to implement the dynamic logic and capacitive storage features in the static logic FPGA?

      Also, what discrete transistors did you use in the model you built for the museum?