Wednesday, September 12, 2012

Easing the interface problem

Re-creating the i4004 CPU is a fun project, but the proof is in creating a running system of some sort. The obvious target is a replica of the Busicom calculator, especially since the firmware for it is available.

The thought of re-creating another set of chips — 4001s, 4002s, and 4003s — really isn't appealing. Nor is developing a bunch of discrete glue logic for modern RAMs, ROMs and I/O ports. Not when there's an easier, more flexible approach: a small FPGA. Unfortunately, the days of 5V FPGAs is past; most will do 3.3V but internally use 2.5V or even 1.2V. That means adding level converters, just like on the test jig.

That got me thinking... the FPGAs use one voltage for the core logic, and a different voltage for the I/O circuits. Why couldn't I do the same on my i4004 replica? All the external I/O interfaces are on one board, and it'll be the last board I make. If I connect the drains of the high-side FETs to a separate Vio pin, I should be able to run the I/O interfaces at 3.3V while the rest of the i4004 runs at 5V. That'd make it easier to work with.

Unfortunately this won't work for the test jig, which uses FPGA logic to drive and monitor internal signals. I have 25 FDV301s already mounted on "Surfboard®" adapter boards, and another 40 Surfboards as yet unused, with less and less need for them. I might as well put them to use protecting the Spartan-3E reference board.

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