I did a bit of work on the test jig last night. First I wired up the GND and +5V pins on the J1 connector. Then I temporarily connected the I/O pin carrying the SYNC output from the FPGA board to the ~CN pin on the inter-board connector through a 470 ohm resistor. This pin connects to a single inverter (an FDV301 FET and a 4.7K resistor), and would allow me to see what effect the series resistor would have on a signal.
I plugged the test jig into my FPGA board, and was rather alarmed to see that even with the power switch in the "OFF" position the FPGA board was feeding +5V through the expansion connector. Examining the schematic I found that the power switch controls a signal input to the regulators on the board and doesn't disconnect the +5V input or the feed to the expansion board. I consider that a design error. It also heightens my worries about driving +5V into an unpowered FPGA I/O pin, even through a resistor. I may have to put FETs or other level converters in series with all the connections on the test jig.
After wrestling a bit with Impact, Xilinx's FPGA loader program, I got the FPGA loaded. The output drivers are still set to FAST (something I ought to change) so there were sharp peaks on the leading and falling edges of the output. On the other side of the resistor, though, there were no sharp peaks, and only a little bit of rounding and no loss of amplitude.
Even better was the signal on the output side of the inverter. On the breadboard, the fast turn-on of the FDV301 causes significant ringing, with the initial excursions reaching -1V and +0.7V. I see none of that on the real PCB. I expect this is because the source lead is now connected to a true ground plane through a very short via and thermals, rather than comparatively long wires.
I didn't have the rest of the signals that feed into the INH circuit connected, and the ~CN pin needs to be connected to the proper source, so I haven't seen the rest of the circuit function. I'll get to that another night.