Last night I re-verified the results of my earlier tests of using a FET as input protection for the Spartan-3E FPGA board. This time, though, I specifically looked at what happens when the gate voltage drops to zero.
While feeding a strongly-driven more-or-less square 5V signal into the drain lead of the FET, I brought the gate voltage down to zero while monitoring the voltage on the source lead. At zero I see a weak ghost of the input signal with an amplitude of about ±200 mV. That's not enough to turn on the protection diodes, so it should be safe. Even when powered (and why would the gate voltage ever be zero while the FPGA is powered?) this still counts as a zero input.
With the gate held at 3.3V, the output at the source lead is clamped to 2.8V, a half-volt drop. The minimum Vih for LVCMOS33 inputs is 2.0V, giving a 0.8V noise margin which should be plenty.
The test jig for the IP board drives all the internal signals except for the four data lines, but once I get to the Instruction Decode and ALU boards this situation will reverse. I think it makes sense to go ahead and put FETs in line with all the signals now (except CLK1 and CLK2, which are already buffered) to avoid major reworking of the jig later. I may just do all 40 lines in two rows of 20 to make it consistent.