I finished coding the Arithmetic/Logic Unit (ALU) board in Verilog. The result is surprisingly compact: just 218 lines, if you ignore blank lines and comments. The Instruction Decoder board only required another 239 lines of Verilog.
Since one of my goals is to really understand how everything works, rather than just doing a rote translation, it took longer than it might otherwise. There are still pieces that aren't clear to me, though. It didn't take long to recognize that there's a carry prediction stage before the actual adder, but I don't understand why the even bits (0 and 2) use positive logic while the odd bits (1 and 3) use negative. Google had one hit that indicated that doing so had speed advantages, but the link led to an IEEE paper that I didn't feel like paying $20 to read. I haven't really dug deeply into the adder either. When I understand these more clearly I'll try to write them up here.
I already understand the operation of the two DRAM arrays, and I'm guessing I can have them re-coded in a few evenings. The timing logic I'm already using to drive the test jig. To make a system that will execute the test program provided as part of the simulator I'll need to implement the 4001 ROM/GPIO chip, and maybe the 4002 RAM/GPO chip.
Maybe I'll see the 4004 running in an FPGA sooner than I expected.
Since one of my goals is to really understand how everything works, rather than just doing a rote translation, it took longer than it might otherwise. There are still pieces that aren't clear to me, though. It didn't take long to recognize that there's a carry prediction stage before the actual adder, but I don't understand why the even bits (0 and 2) use positive logic while the odd bits (1 and 3) use negative. Google had one hit that indicated that doing so had speed advantages, but the link led to an IEEE paper that I didn't feel like paying $20 to read. I haven't really dug deeply into the adder either. When I understand these more clearly I'll try to write them up here.
I already understand the operation of the two DRAM arrays, and I'm guessing I can have them re-coded in a few evenings. The timing logic I'm already using to drive the test jig. To make a system that will execute the test program provided as part of the simulator I'll need to implement the 4001 ROM/GPIO chip, and maybe the 4002 RAM/GPO chip.
Maybe I'll see the 4004 running in an FPGA sooner than I expected.
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