Voltage protection, not conversion

While the series resistors would probably serve the function of limiting the input voltage to the FPGA to a non-damaging level, I'm really not happy with that solution. If the i4004 boards are powered before the FPGA, the resistors need to drop about 4 volts instead of 1.7, and that would drive the protection diodes pretty hard. The back-flow of current into the Vcco supply could disrupt the required power sequencing, and all hell could break loose. I really don't want to damage the Spartan-3E reference board.

While re-reading Xilinx Application Note XAPP459, I noted that they mention the use of "FET switches" for level conversion. I've done this with I²C buses, but had dismissed that option here for some reason. The obvious thing was to try it on the breadboard!

My test setup has the input of the FET driven by my trusty PIC, the FET's gate hard-wired to 3.3V, and the output connected to an FDV301 set up as an inverter. First I tried using a BSS83 with the substrate tied to ground. That didn't work too well, with a crisp 3.3V input signal showing up on the output as a somewhat ragged 1.6V signal. That pretty much vetoes running the boards at 3.3V as well.

Swapping in an FDV301, though, worked much better. Driving the drain with a signal between 4.5V and 6.0V results in a nice flat 3.0V output at the source with good rise and fall times and very little propagation lag. As the input drive drops the output level tracks down with about a 0.6V difference. Still, the FPGA considers anything above 2.0V as a valid "high" which leaves plenty of margin. This doesn't appear to adversely affect the input signal. Flipping things around to drive the source to 3.3V also gives a nice output at the drain with less than a half-volt loss, even when driving a 330pF load. If the i4004 circuits allow it (in other words, if they don't depend on the bus capacitance to store a level) I could add a pull-up resistor to 5V on the high side and get full-swing outputs.

What happens when the FPGA is powered down while the i4004 boards are powered up? Since the FET's gate is connected to the FPGA's +3.3V supply, the FET should stay turned off with no back-flow into the FPGA or supply. If the FPGA is powered up while the i4004 boards are powered down they'll see 3.3V but they can handle that: the FDV301 is the worst case with a Vgs of 8.0V maximum.