Test jig preparation

One of the issues with using the Spartan-3E to drive the test jig is voltage: my i4004 boards are designed to run on +5.0V, while the FPGA uses +3.3V and is not 5V tolerant. The Spartan-3E's maximum input voltage is a hair over 4V, beyond which the circuits may suffer damage.


It's possible that the i4004 board could run at 3.3V, but all my experiments have been done assuming 5V. The FDV301 transistors are specified to turn on at 1V, and they certainly do that. The BSS83, though, is vaguely specified as turning on somewhere between 0.1V and 2.0V, and in my usage it appears to turn on at about 1.4V.

When the BSS83 is used as a transmission gate, the Gate lead is pulled high to allow a signal to pass. With the Gate at +5.0V, a 3.3V signal passes very cleanly with very little propagation lag. Above that, the decreasing difference between the Gate and the Source/Drain causes it to start acting like a resistor, with all the RC circuit effects. If the Gate were only pulled up to 3.3V this effect would start around 1.6V, which doesn't leave much in the way of noise margin.

So that probably wouldn't work well. Instead, I'm left with the problem of gluing 3.3V and 5.0V logic together.

First I looked at the two clock lines, CLK1 and CLK2. These are critical. Both are frequently used to control transmission gates, so it's important for them to reach the full 5.0V quickly and cleanly. Further, these signals run everywhere on all boards: CLK1 connects to 28 devices, and CLK2 connects to 51. That's a lot of capacitance to drive.

A while back I designed a board to host an Intel 8080A CPU. Although it's primarily a 5V device, the 8080A requires two 12V clocks with strict rules on rise-time. As part of that project I'd identified several chips designed to drive exactly this sort of circuit. While driving only to 5V isn't a challenge for these chips (in fact, they aren't specified to operate below 4.5V) I happen to have a couple of them on hand. Free (or, already paid for) is always a good price!

A review of the datasheet for the Microchip TC4427A driver shows it needs only 2.4V input drive, and a run on the breadboard confirmed it. The only issue is that with such a low output drive voltage the propagation lag is about 75ns, twice what the datasheet claims, but I can make allowances for that in the FPGA coding. Driving an artificial 330pF load, I see a nice, clean rise to very close 5V with little overshoot, and a mirror image on the falling side. The TC4427A is also symmetric in its propagation lag, which is nice.

The second step is the other signals the FPGA drives. Fortunately, both of the transistors I'm using are happy with 3.3V drive, so that's a no-op.

The third, and most worrisome, challenge are the four bidirectional data lines. These need to be driven high enough that the 5V circuitry is solidly turned on, while not allowing the FPGA inputs to be damaged. I spent far too many hours browsing the available bidirectional level shifter ICs before determining that none would be easy to use. The problem is that they're all SMDs, and that means adapter boards. The best compromise I found was four 65-cent single-bit ICs, soldered to four $1.95 adapter boards. Maybe I could do without the level shifters?

The receivers on these lines are gated through BSS83s in transmission gate configuration, and I was worried that 3.3V drive would be attenuated to the point where it wouldn't be high enough. A few trials with the breadboard allayed that fear: the BSS83 passes a 3.3V signal essentially unattenuated and un-delayed, and both types of transistor are happy with 3.3V drive. So all appears good when the FPGA is driving the data bus.

What about when the i4004 boards are driving the bus? The data bus is driven by two different types of circuits. Some of the drivers are push-pull which drive very strongly at about 4V, while others are simple resistive pull-ups that drive weakly at 5V. All are gated onto the bus with BSS83 transmission gates. This leaves between 0.7V and 1.7V to be dropped before reaching the FPGA. Some research showed that the Spartan-3E has protection diodes between all I/O pins and both ground and supply. These are rated to tolerate 10mA, and there is an application note describing how to take advantage of this when interfacing to higher-voltage logic.

To make a long story short, I believe I can use a resistor to drop the excess input voltage without significantly affecting the output drive level. A 470 Ohm resistor would keep the diode current below 5mA even with 5.5V coming from the board. When driving the board it will limit the current to 7mA, but calculations suggest a circuit that will work with a 2.2K pull-up to 5V will be quite happy with 470 to 3.3V. This will clamp the bus drive from the weaker drivers at about 3.3V, but I don't think that will be a problem. And if it is, I'll change the test jig.

Now all I need is a board to test!