FPGA Power-On and External Reset

As I whittle down the list of things that need fixing before sending my PCB out for fabrication, I came to the question of how to make sure the FPGA resets cleanly on power-on, and how to force a reset externally.

The Xilinx Spartan 6 avoids many of the requirements for strict power-on sequencing by including an internal power-on reset circuit. This holds the reset of the FPGA circuitry in reset until all three power buses (Vccint, Vccaux, and Vcco2) reach operating levels. However, this requires the power supplies to meet certain ramp timing: the supplies must ramp up monotonically and must reach operating levels in 0.20 to 50.0 milliseconds.

Although the LTC3607 voltage regulator I'm using provides a couple of graphs showing start-up characteristics, I won't know exactly what the power-on ramps look like until after the board is fabricated and assembled. My plan was to sequence the 1V2 (Vccint) supply to turn on only after the 3V3 (Vccaux and Vcco2) supply was on and stable. This would allow the 3V3-powered Flash ROM time to complete its power-on reset before the FPGA could begin to access it. If the 1V2 supply ramps up cleanly I'd expect this to be sufficient to cleanly reset the FPGA, but I'm not confident enough to leave it at that.

Another consideration is how to force a reset externally. For this I provide a tact switch mounted behind the hole provided by the P170-DH shell for this purpose. I created a simple circuit connecting this switch to the pull-up resistor on the PROG_B input to the FPGA. Pulling this input low causes the FPGA to reset internally, and its release allows the FPGA to begin loading from the Flash ROM.

This circuit always worried me, though, as it provides no debounce for the mechanical reset switch. I could connect a capacitor between the RESET net and ground, but then the PROG_B input would rise slowly and the FPGA does not document any sort of hysteresis on its inputs. It does, however, document a minimum pulse width, which could be violated if the switch bounces on release (apparently this is a real behavior). I need for this circuit to drive a device with a Schmitt trigger input.

The LTC3607 provides a "Power Good" output from each of its two regulators, and I considered connecting the PG pin from the 1V2 regulator to the PROG_B input. But there's a hitch: when the RUN input to the regulator is low (i.e. the regulator is turned off), the PG output has a resistance of up to 700 ohms. The PROG_B input has an internal pull-up to Vcco2 (3.3V) that can source as much as 500 uA, and the 4.7K pull-up resistor (the suggested value) in the external reset circuit sources another 700 uA. The voltage drop of 1.2 mA across a 700 ohm resistor is 0.84V, which is too high to drive the FPGA into reset reliably.

I needed some way to combine the external reset circuit with the PG output while driving the PROG_B input cleanly. Browsing the available parts I discovered that the 74AUP1T08 2-input AND gate has Schmitt trigger inputs. Thus I replaced the reset circuit shown above with a new circuit:

You might ask where I got the values for the two resistors and the capacitor. These are derived from the formulas nicely presented by Jack Ganssle's article A Guide to Debouncing - Part 2 and the datasheet for TI's SN74AUP1T08. They are calculated to tolerate a 20 millisecond bounce time on both switch actuation and release. I don't expect to use this switch very often, but it's worth it to me to do it right.