P170-DH replacement PCB progress

As I've said before, I have to be in the right mood to do printed circuit board layout. If I try to force it I'm quite capable of staring at the problem for hours without making any progress. Fortunately, this is a hobby project and no one is looking over my shoulder. Except maybe those who read this blog.

When the proper mood strikes, though, I can make great strides in a short period. This week has been one of those periods.

The primary issue has been getting tracks routed out from the FPGA. The Spartan 6 comes in only one hobbyist-friendly package: a 144-pin TQFP (thin quad flat package) whose pins are spaced 0.5 mm apart. Including the pins ("fingers" might be a better description) this package is 22mm square. I've laid out boards with similar packages before, but this board presents special challenges.

The biggest challenge is that positioning of the FPGA is dictated by the design of the Canon P170‑DH calculator shell. The bottom side of the board has contact patterns placed in fixed positions for the conductive-pill keyboard and slide switches; no tracks or vias can be placed on the bottom layer in the areas they occupy, and no components can be mounted on that side because of the rubber sheet supporting the pads. There are also support ribs on the bottom half of calculator shell that help support the PCB against flexing caused by key presses; these press against the top side of the PCB so no components can be located in those areas. Finally, there are mounting holes for the screws that hold the PCB to the top half of the shell.

All of these fixed features mean there is very little open space for mounting something as large as this FPGA. It would have been a lot easier to find space for the 8mm square BGA package, but with a ball pitch of only 0.5mm there was no way I could attempt that. Eventually I settled on orienting the FPGA behind one of the keypad patterns so vias could be placed both inside and outside the rows of pins without penetrating the contact pattern. The original idea was to have the keypad pattern centered, but a mounting screw hole forced the FPGA off-center, where it crowds the nearby keypad patterns.

The Xilinx Spartan 6 is a very fast device, capable of operating with a clock frequency of 667 MHz. Even when operated with a slower clock power supply bypassing is critical, so the first things I placed were the bypass capacitors. Research found people having success using 4.7uF multi-layer ceramic capacitors in 0402 packages, so I placed one of these close to each of the power pins. Yes, I'll hate myself later for doing this, but 0603 packages reportedly don't perform as well and would have made routing nearby pins even more difficult.

The second thing I placed was the bootstrap Flash ROM, whose connections I've commented on repeatedly. What should have been third was the JTAG connector, though eventually it found itself an almost perfect spot in the shadow of the nearby mounting screw hole.

Routing tracks from the top and right side was fairly easy and those sections were mostly complete months ago. These went to the debug connector, the serial interface, and about half of the vacuum fluorescent display drivers. But I stalled on the bottom and left edge for months.

Over the summer I decided to move the power subsystems to the same side of the board as the FPGA to make it easier to mount components and probe the circuits during testing. Then I decided to "flip" the board so the keypad contacts were on the bottom layer rather than the top to make routing easier. Even though KiCad can display the board "flipped" without doing this, the layer order doesn't flip (yet -- it's on the enhancement list) so I was always routing behind other tracks.

I'm not sure what changed, but this week it the problem of routing the left edge of the FPGA seemed to be a lot simpler. I moved the clock oscillator module connection from the bottom edge to the left, and  moved the keypad row Schmitt Trigger inverters away from the bottom edge. This opened up space for routing the keypad column outputs and row inputs along the bottom edge.

Here's the state of the board as of last night:

I'm down to only 181 unrouted nets, most of which are already routed away from the congestion of the FPGA pins and heading in the correct direction. I don't want to jinx myself, but with any luck I'll be assembling this board by late December.