One of eight channels of the PmonLVLSHFT circuit |
There is a pull-up resistor on the B-side I/O port, but it's 100K and intended only to keep the input from floating. To get a half-volt noise margin I'd need the B input to reach 4.0V. With a 570 ohms in series on my board and 270 ohms on the S3E board, the pull-up resistor would have to be 1.2K, not 100K. With a 1.2K pull-up, the S3E wouldn't be able to pull the SN74LVC1T45's input below its 1.5V maximum input-low threshold. That wasn't going to work.
What about treating the S3E output as an open drain rather than driving it high? That would work as far as voltage levels are concerned, but the 100K pull-up would result in a slow rise time. Disregarding the capacitance of the cable and connectors the pull-up is looking into 33pF, making the rise time from 0 to 4.0V over 5us. That might work for 9600 bps async with a bit time of 104us, but it's over 60% of the 8.7us bit time at 115200 bps.
Reducing the pull-up resistor from 100K to 10K seemed the logical solution. Even with a 60pF load the rise time to 4.0V is less than one microsecond. Pulling this to ground draws only 0.5mA so I won't be stressing any drivers. Through ordering goofs I happen to have several hundred 10K 0603 SMD resistors on hand. I didn't even bother attempting to test operation with the 100K pull-ups before changing them to 10K.
A manager I once had the misfortune to work with used to close her meetings by demanding of the attendees, "Is there anything we haven't thought of?" Somehow she never saw the irony in this question. (Nor, somehow, did she appreciate my "Yes, but I don't know what" replies.) There's always something we haven't thought of, even after more than a year planning as I have on this project. The best one can hope for is that the changes that need to be made to address the things we haven't thought of aren't too painful. Thus far that hasn't happened on this one.
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