Spice simulation of the External I/O

I got to wondering how accurately my "back of the envelope" calculations modeled the External I/O interface circuit. So I set it up in LTspice:

This isn't a simple RC circuit, so I'll explain:

• V1 is the +5.0 supply to VCCB, sourced by the Spartan-3E Starter board through the PS/2 interface.
• R1 is the pull-up resistor on my P170-DH replacement PCB.
• C1 is the capacitance of the SN74LVC1T45 B input pin.
• R2 is a 470Ω current-limiting series resistor on my board.
• R3, C2, and C3 model the TPD4F003 EMI/ESD protection filter.
• R4 is a 270Ω current-limiting series resistor on the S3E Starter board.
• C4 is the capacitance of the Spartan-3E input pin.
• D1 is the Spartan-3E pin's internal protection diode to Vcco.
• V2 is the Spartan-3E's  Vcco supply (+3.3V).
• S1 and V3 model the Spartan-3E's output pull-down FET.

Whew! Now let's look at the transient analysis of this circuit. Initially S1 will be closed, simulating the S3E driving its output low. After 1.0µs S1 will open, and we can observe the rise-time of the input to the SN74LVC1T45's B input pin (identified as "V(b)").

Here is the simulation with R1 at 100K:

With SW1 closed, the B input pin sits at 41mV. With a VCCB of 5.0V, the SN74LVC1T45's input-low threshold is 1.5V, so this is fine. SW1 opens at 1.0µs and things start to change. The B input only crosses the 3.5V input-high threshold after 5.35µs, and stabilizes at 3.7V after 6.25µs. That's a long time with only 200mV noise margin.

Why doesn't this voltage rise higher? The Spartan-3E has a clamp diode between each of its input pins and the I/O source voltage Vcco. This clamp diode, modeled here with D1, is sinking current once the S3E pin rises high enough. Although we usually think of silicon diodes as having a forward voltage drop of 0.7V they often begin conducting at low currents at a much lower voltage. I chose the 1N914 out of convenience and it may not match the behavior of the S3E clamp diode exactly, but I didn't feel like ferreting out the S3E IBIS characterization. For the purposes of this simulation I think it's probably close enough.

A 200mV noise margin is kinda iffy for single-ended signaling across an uncharacterized cable, and the rise times are too slow to give reliable results with high bit rates. But it might have worked at 9600 bps.

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Now let's look at this same circuit with the pull-up resistor, R1, changed to 10K:

Initially the B input pin is at 388mV. This is higher than with the 100K pull-up, reflecting the increased current through the resistors downstream of the B input pin, but still far below the 1.5V threshold.

After SW1 opens at 1.0µs the voltage at the B input pin rises much faster than with the 100K pullup, and I've changed the horizontal scale to make the plot more informative. After only 425ns it has passed the 3.5V input-high threshold, and by 600ns it has reached 3.87V. Somehow I thought this would reach my 4.0V target voltage, but I underestimated the effect of the clamp diode. A 370mV noise margin should be sufficient given that the 3.5V threshold is a maximum and the typical is likely to be lower.

What's the effect of changing the pull-up resistor to a lower value than 10K? Here's another LTspice run, stepping the resistance of pull-up resistor R1 from 2.2K to 10K:


Both screenshots show the same data, with one showing the full graph and the other with the vertical axis scaled to show the graph only from the 3.5V input-high threshold up.

Although reducing the pull-up resistor reduces the rise-time to the 3.5V input-high threshold, it doesn't provide that much improvement in noise margin. The difference between the 10K resistor and the 2.2K resistor is barely 300mV. The 2.2K resistor tops out at 4.16V, but barely squeaks under the 1.5V input-low threshold; a 1.0K resistor wouldn't pull even that low. 

These simulations suggest the 10K resistors should pull high enough for reliable signaling, with rise times short enough to allow for higher bit rates. At 115200 bps a single bit lasts for only 8.68µs, with a x16 start bit sample occurring every 543ns. The 10K pull-up should be fast enough for this. If I have trouble with noise margins or timing jitter using the 10K pull-up I'll try 4.7K resistors. This would raise the noise margin to my arbitrary 500mV target and further reduce the rise-time, but I'm not inclined to change the resistors again unless I have to.