Tuesday, May 5, 2020

Another bug? I FIN you not

The FIN instruction is supposed to fetch the contents of the ROM location specified by the scratchpad R0R1 register pair, and store those contents into another scratchpad register pair. Obviously this didn't work properly or I wouldn't be writing about it.

Thus far I've found two types of problems. The first and most common is a translation error when writing Verilog HDL to match the schematics. This clearly requires a code change to correct the erroneous behavior.

The second type of problem is an uninitialized signal that causes the simulation to fail, but would have worked in hardware. A good example of this is where the uninitialized signal is, at some point, ANDed with another signal whose value is false, or ORed with another signal whose value is true. In hardware, the AND would give a false result, and the OR would give a true result. The simulator, on the other hand, gives an unknown (or X) result in both these cases.

The failure of the FIN instruction was a result of logic that was completely missing from the Verilog code. I'm not entirely sure how that happened, though I have a guess.

When I partitioned the i4004 CPU design among the five boards I had planned, I generally tried to put the circuits where they made the most sense. But I also wanted to minimize the number of inter-board connections. The structure of my Verilog code follows that partitioning.

Clearly some of the missing logic belonged on the Instruction Decode board, because it needed to have access to all four bits of the OPR register, as well as the low-order bit of the OPA register. Yet the rest of the logic seemed to fit better with the scratchpad logic. My best guess, eight years later, is that I wasn't sure where to place the logic for this signal and ended up forgetting about it.

Just for sanity's sake I fired up Eagle and checked the partitioned schematics. The logic exists in the schematics and in the partially-completed board layouts, and is partitioned as described above. The fix to the Verilog follows the hardware, of course.

And now it FINs with the best of them.

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