XST conditional synthesis with Verilog generate

One of the purposes of creating my MCS-4 Digital Clock was to come up with something that would run on my hybrid debugging setup and give a clear indication of proper operation. This setup is the Digilent Spartan-3E Starter reference board connected to an expansion card that serves as a carrier for my i4004 CPU boards. This allows me to run the as-yet unimplemented parts of the i4004 CPU in the Spartan-3E FPGA.

To do this I created a Verilog module representing the i4004 CPU with instantiation parameters that allow me to "cut out" the parts that are implemented in hardware. The Xilinx XST toolchain supports the Verilog generate statement, including the use of if statements to include or exclude portions of code. Note this is different than using the preprocessor `define and `ifdef statements.

I read some seemingly definitive articles that said the actual generate and endgenerate statements are optional, so I left them out. XST complained that my if statement was unexpected, as it was outside of an always or initial block. Adding the generate and endgenerate statements fixed that, so either XST doesn't know that these are optional, or perhaps they're only optional in SystemVerilog (some articles I've read seem to assume everyone is using SystemVerilog now, and just refer to it as Verilog).

With that taken care of, I noticed that XST seemingly wasn't responding to the value of the instantiation parameter. That is, this didn't work:

generate
if (~IP_BOARD) begin
    . . .
end
endgenerate

By experimentation I found this did:

generate
if (IP_BOARD == 0) begin
    . . .
end
endgenerate

I always love figuring out legal (or accepted) syntax by trial and error!